Synopsys公司发布DFM新系列产品

全球领先的电子设计自动化(EDA)软件工具领导厂商Synopsys推出了具备工艺识别功能的可制造性设计(DFM)新系列产品PA-DFM,用于分析45纳米及以下工艺定制/模拟设计阶段的工艺变异的影响。随着工艺尺寸的日益减小,先进硅技术将引起更多如应力工程的变异问题,这将越来越影响电路的性能。Synopsys PA-DFM系列的核心产品Seismos和Paramos可将制造变异信息反标回设计阶段,帮     

亚100纳米级标准单元的可制造性设计

本文介绍了亚100纳米工艺可制造性验证的一组工艺仿真和错误定位技术,制定了标准单元可制造性设计(DFM,Design For Manufacturability)的流程,重点讨论了在亚100纳米工艺条件下标准单元设计中遇到的一些典型可制造性问题,提出了相应的新设计规则和解决方案.依靠以上DFM技术方法,完成了实际90nm工艺标准单元可制造性设计工作.     

SOC芯片设计与测试

SOC已经成为集成电路设计的主流.SOC测试变得越来越复杂,在设计时必须考虑DFT和DFM.本文以-SOC单芯片系统为例,在其设计、测试和可制造性等方面进行研究,并详细介绍了SOC测试解决方案及设计考虑.     

PCB制前DFM概述

PCB制造是个复杂的系统性工程,包含CAD设计、制前DFM、生产控制、性能测试等方面,环环相关,缺一不可。而随着PCB技术不断的发展,在满足PCB越来越高性能要求的同时,如何提高PCB可制造性以利于生产成本的降低显得尤为重要。本文以PCB制造生产前客户资料DFM设计为着重点,分别从PCB设计数据的导入、制前客户设计优化处理、生产控制流程及参数的设计等方面进行阐述,展示PCB制造从CAD设计图纸到生产信息的转换过程,解析制前设计优化处理的必要性及对生产的影响,以促进及改善PCB设计者在CAD设计阶段的可生产性设计。     

OPEN FORUM：可制造性设计（DFM）的关键要素

可制造性设计(DFM)不仅对于确保产品与设计的实际生产，而且对于保证其可靠性、可测试性、可返工性及耐用性至关重要。如果能够正确实施DFM，就可以避免与现有制造工艺不一致的设计，避免需要多余步骤或手工工艺的设计。     

TSMC和UMC推出不同的65nmDFM解决方案

TSMC刚推出了一种65 nm可制造性设计(DFM)方案,它是一种柔性设计支持生态系统,采用可制造性统一数据格式,通过精选的EDA工具将DFM能力直接传递至设计人员的工作站。提出这个方案是为了使DFM工具,如,光刻工艺检测、CMP     

SoC、DFM与EDA

介绍了系统级芯片(SoC)、可制造性设计(DFM)和电子设计自动化(EDA)的最新发展动态。SoC正在从单核向双核、四核和多核过渡。SoC设计必须采用DFM和EDA。采用DFM和EDA的优点:(1)提高芯片的生产效率和良率;(2)降低芯片生产成本;(3)缩短芯片生产周期,加速上市。     

文献与摘要(35)

一种提供好方案的可制造性设计流程 DFM:A Process to Provide Best Solutions 本文介绍了可制造性设计(DFM)的流程和运作方式,及其优点。在正式制作印制板之前的DFM可以使客户从技术上和制程能力上对PCB制造商充满信心,好的可制     

业界动态

台积电针对90纳米平台提供更多DFM建议在日前举行的台积电(TSMC)2005年技术研讨会上,该公司的高层透露,将为采用90纳米设计规则的工程师提供更多的可制造性设计(DFM)建议(recommendations)。台积电DFM项目负责人JamesWang透露,此次新公布的6条指导建议基于台积电2004年的技术研讨会上所提出的建议,并延伸到了90纳米平台。这6条建议中,部分建议的细节在本次会议上获得批露。台积电称,其中“最重要的改变”是金属沉积(metaldeposition),裸片的金属沉积必须要相对均衡一致,防止进行到化学机械抛光(chemical-mechanicalpolishing)步骤时出…     

DFM将成为后90 nm工艺中半导体技术的一部分

即使飚升的设计和制造成本也无法阻挡半导体制造向90nm以及更先进工艺进军的步伐,伴随着这一进程的不断加快,可制造性设计(DFM)成为目前最为热门的话题之一。在DFM问题上,业界的对策层出不穷,而许多新兴公司也在不断涌现。不过最被寄予厚望的仍然是拥有大量制造经验的晶圆代工企业。业界专家建议,IC设计师应该加强同晶圆代工企业的合作。两家全球最大的晶圆代工企业已经做出了表率:继去年6月台积电(TSMC)在DAC大会上宣布提供分别名为YieldPlus的免费DFM工具组和YieldPro的DFM收费服务之后,台联电(UMC)也于近期宣布将针对发展90n…     

Variation

Variation afflicts the design, manufacture, and operation of integrated circuits. Techniques and tools are needed in three areas to address variation: statistical metrology, advanced process control, and design for manufacturability. First, statistical metrology seeks to characterize and model variations and their sources. Advanced metrology helps to understand geometric and material property variations, while variation test structures and test circuits enable study of the impact of specific or aggregate variations on performance. Second, advanced process control attempts to reduce process variation through sensing and feedback/feedforward control during fabrication. Third, design for manufacturability (DFM) seeks methods to improve performance and yield given process and environmental variation, through robust design, increased regularity, and other approaches. Finally, linkages between these areas, particularly between statistical metrology and DFM, will be important and empowering.     

Statistical methods for the estimation of process variation effects on circuit operation

In this paper, a technology computer-aided design (TCAD) driven method for accurate prediction of the performance spread of integrated circuits due to process variations is presented. The methodology starts with the development of the nominal process recipe and process simulators are calibrated to an existing process to obtain nominal device characteristics. After determining nominal process parameters, their variations are introduced followed by screening experiments to determine the relative effects of given process variations on the input-output delay and the average power dissipation in a circuit. Response surface models (RSMs) are then generated based on critical process factors identified. Process parameter optimization is performed using these RSM models to tune the mean circuit performance and to improve the yield. This methodology is demonstrated on a 33-stage ring oscillator manufactured with a CMOS design flow. The proposed methodology maps the process domain to design space, and plays a key role in design for manufacturability (DFM) to quantify direct impact of the process variations on circuits.     

超深亚微米与纳米级标准单元的可制造性设计与验证技术

当半导体工业进入到超深亚微米时代后,标准单元的设计面临着新的挑战.由于亚波长光刻的使用,图形转移质量将严重下降.在这种情况下,以集成电路的可制造性作为目标的"可制造性设计"方法在标准单元设计中变得至关重要.本文分析了超深亚微米与纳米工艺条件下标准单元设计中遇到的一些典型可制造性问题,提出了相应的新设计规则和解决方案,完成了实际90nm工艺下标准单元的可制造性设计工作.同时,文中提出了包括光刻模拟、测试电路组等技术在内的单元可制造性设计和验证的流程.     

纳米集成电路 Cu CMP工艺模型参数优化

铜化学机械抛光受几何图形特性如线宽、间距和图形密度的影响,芯片和晶圆上铜互连线厚度的不均匀性都会影响电性能和降低良率。本文从物理化学的角度对CMP工艺进行了回顾和分析,针对Cu CMP制造工艺和在MIT提出的（Pattern-Density Step-Height,PDSH）模型基础上,建立与工艺相对应的三步骤工艺模型。为了扑捉工艺与版图结构的相关性,设计了一款65纳米测试芯片并在SMIC完成工艺实验。按照模型参数提取流程,通过芯片测试数据提取模型参数和验证工艺模型。模拟结果与测试结果对比说明二者趋势完全一致,最大偏差小于5 nm。第三方测试数据进一步证明模型参数优化取得很好的结果。精准的Cu CMP工艺模型可以用于做芯片的DFM检查、显示和消除关键热点,从而确保芯片的良率和集成电路量产能力。     

Routing for manufacturability and reliability

As IC process geometries scale down to the nanometer territory, industry faces severe challenges of manufacturing limitations. To guarantee high yield and reliability, routing for manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this article, we introduce major routing challenges arising from nanometer process, survey key existing techniques for handling the challenges, and provide some future research directions in routing for manufacturability and reliability.     

Use of short-loop electrical measurements for yield improvement

Modern submicron processes are more sensitive to both random and systematic wafer-level process variation than ever before. Given the dimensional control limitations of new technologies, the amount of wafer-to-wafer and within wafer nonuniformity of many steps is becoming a significant fraction of the total error budget, which already includes the usual step-to-step allocations. However, a significant portion of the total observed variability is systematic in nature. Accordingly, particle defects may not continue to dominate parametric yield loss without improved understanding of parametric variations. In this paper, we demonstrate the use of short-loop electrical metrology to carefully characterize and decouple wafer-level variability of several critical processing steps. More specifically, we present our method and give results obtained from variability analyses for lithography critical dimension (CD) and inter-level dielectric (ILD) thickness control. Using statistically designed experiments and dedicated test structures, the main factors affecting dielectric thickness variability has been identified. The systematic variability from a wafer stepper has been extracted using a physically based statistical data filter. Once isolated, the deterministic variability can be modeled and controlled to enhance process and circuit design for manufacturability (DFM). We hope that in the future this work will be coupled with novel DFM-oriented CAD tools that encapsulate this information in a fashion that makes it useful to process and circuit designers     

Review and Perspective of Architecture Development for Dynamic Random Access Memory

Discussed is a review and perspective of architecture, materials and process technology for dynamic random access memory（DRAM） applications. Key challenges of the transistor and capacitor scaling from DRAM will be reviewed. To continue scaling down, multi-gate devices with very thin silicon channels are most promising. Several architectures like Fin-field effect transistor（Fin-FET）, Wafer bonded double gate and silicon on nothing（SON） gate-all-around have been demonstrated with good electrical characteristics. An overview of the evolution of capacitor technology is also presented from the early days of planar poly/insulator/ silicon（PIS） capacitors to the metal/insulator/metal（MIM） capacitors used for today 50 nm technology node and below. In comparing Ta2O5 , HfO2 and Al2 O3 as high-k dielectric for use in DRAM technology, Al2 O3 is found to give a good compromise between capacitor performance and manufacturability used in MIM architecture.     

用在可制造性设计中的光刻规则检查

可制造性设计(DFM)已经发展成为优化通晓制造技术设计中的有效工具,它包含从理论、规则到工具的整体应用来提升从设计到硅片的流程.基于制程模型的光刻规则检查(LRC),可查出没被设计规则检查(DRC)出来的设计布局的不足之处.本设计把光刻规则检查加入到设计流程中,用来优化设计规则,改善布局更有利光学邻近效应修正,使布局图形有更大的制程窗口.     

表面组装印制电路板的可制造性设计

表面组装印制电路板的可制造性设计主要解决电路设计和工艺制造之间的接口问题.可制造性设计具有缩短开发周期、降低成本、提高产品质量等优点,是企业取得成功的有效途径.从介绍表面组装印制电路板常见的不良设计入手,进而分析不良设计产生的原因,最后从设备和工艺两个方面提出可制造性设计的具体要求.