Determining the drain doping in DMOS transistors using the hump inthe leakage current

The hump in the leakage current of double-diffused metal-oxide-semiconductor (DMOS) transistors observed for low drain voltages is explained. This hump is due to surface generation current of the gate-controlled diode formed by the base-drain p-n junction. The drain bias of the DMOS transistor is shown to have the same effect on the charge at the drain surface as the body bias in the conventional MOSFET. The body effect is used to develop a new method for determining the drain doping in DMOS transistors. This method is nondestructive, and does not require special test structures. Instead, electrical measurements are performed on conventional DMOS transistors. The method is ideally suited for determining the doping in the drain region of interest. Specifically, in DMOS transistors in which a surface implant is used to reduce the on-resistance, the method provides the doping concentration in the implanted region. In DMOS transistors which do not have the surface implant, the method yields the doping concentration in the drain epitaxial layer. In this study, the method is illustrated by determining the drain doping for six discrete power MOSFET device types from three different manufacturers     

Experimental derivation of the source and drain resistance of MOS transistors

A new method for experimentally deriving the source-and-drain resistance of MOS transistors is presented along with experimental results verifying its accuracy. The method also yields the mobility reduction with high gate-oxide field. The measurements are done on two (or more) MOS transistors which are identical except that their gate lengths differ by a known amount.     

An efficient method for determining threshold voltage, seriesresistance and effective geometry of MOS transistors

An accurate and robust method of extracting the threshold voltage, the series resistance and the effective geometry of MOS transistors is presented. The method is based on efficient nonlinear optimization using an iterative linear regression procedure which usually converges in less than four rounds. Thereby extracted parameters are obtained from analytical expressions for the solutions to a linear system of equations whereby time consuming numerical differentiations are avoided. MOSFET parameters are explicitly identified as parameters of an underlying widely used device model that is a good approximation for operation in the linear region. The method is particularly suitable for process characterization and can be used on as few as twelve data points (three data points from each of four different size transistors). By connecting external resistors in series with the transistors, we show that the extracted values of the parameters are independent of the series resistance     

超高速VLSI中多晶硅发射极晶体管串联电阻的测量

本文对目前流行的测量晶体管串联电阻的常规方法进行了理论分析和实验验证，结果表明，用常规方法测量多晶硅发射极晶体管串联电阻的误差很大。     

Collector recombination lifetime from the quasi-saturation analysisof high-voltage bipolar transistors

A novel method of measuring the collector recombination lifetime, which is independent of emitter effects, is presented by extending the quasi-saturation analysis of high-voltage bipolar transistors to the high-current-density regime. The technique is supported by theory, and experimental results are presented on transistors fabricated with different emitter properties. This is a nondestructive method and gives the lifetime values at the current densities normally encountered when the transistor is in actual operation. The values for the collector recombination lifetime obtained by the present method are independent of the properties of the emitter region     

Measurement of the low-current base and emitter resistances of bipolar transistors

A new ac method is proposed to measure the emitter and base resistances of bipolar transistorsat low current levels at which the effective transistor geometry is given by the processing and is unaffected by the changes induced by high currents. The technique is based on a measurement of the input impedance at frequencies below about 50 MHz. It is particularly suited for the measurement of the physical emitter resistance of scaled transistors. The method is illustrated on microwave transistors with metal contacts and on self-aligned digital transistors with polysilicon contacts. A comparison of the results obtained using this method with those from dc methods operating at high currents can be used to explore the current dependencies of the resistances. The technique is applicable both for homojunction and heterojunction transistors.     

Method for determining the emitter and base series resistances of bipolar transistors

A simple method for determining both the emitter and the base series resistances of bipolar transistors from the measured I - V characteristics is described. The method is based on the observation that deviation of the base current from the idealexp (qV_{BE}/kT)behavior at high currents can be attributed solely and relatively simply to series resistances. Series resistances determined by this method are given for sample high-speed digital bipolar transistors.     

Molten-diffused silicon transistors

While the author was engaged in the study of producing single crystals for high-frequency transistors based on the conventional grown-diffused process, it was found highly difficult to produce by this method single-crystal material with uniform base width less than a few microns. The disadvantage of the conventional grown-diffused process could be eliminated by using a new method in which impurities are diffused from the molten semiconductor directly into the single-crystal bulk. This single-crystal-producing method was given the name “molten-diffused process”. With the application of this process, it has become possible to obtain silicon transistors with a base width less than 1 μ and a cut-off frequency of 580 Mc/s. This paper reports on the transistors so produced.     

单层硫化钼的研究进展

单层硫化钼(MoS2)是具有直接帯隙1.8 eV的二维半导体,因其特殊的六方晶系层状结构,而具有优异的物理和化学性质。简要介绍了MoS2材料的几种主要制备方法:如高温硫化法、水热法以及表面活性剂促助法等,讨论了各种制备方法在国内外的研究现状及优缺点。给出了单层MoS2在晶体管、集成电路、逻辑运算等方面的一些应用。与硅晶体管相比其晶体管体积更小、更省电,并可减少短通道效应,电流开/关比例高于1010。这些应用说明了其可被广泛应用于未来的纳米电子器件。最后,对MoS2未来的发展方向进行了展望,认为工艺制备方法有待进一步改善,单层MoS2的应用领域也有待进一步深入拓展。     

Impact of injection limitations on the contact resistance and the carrier mobility of organic field effect transistors

The contact resistance as well as the mobility have developed to key performance indicators for benchmarking organic field-effect transistors. Typically, conventional methods for silicon transistors are employed for their extraction thereby ignoring the peculiarities of organic transistors. This work outlines the required conditions for using conventional extraction techniques for the contact resistance and the mobility based on TCAD simulations and experimental data. Our experimental data contain both staggered and coplanar structures fabricated by exploiting different optimization techniques like SAM treated electrodes, different shearing speeds, PS blending and silicon oxide functionalization. In addition, the work clarifies how injection limited current–voltage characteristics can affect high-performance organic field-effect transistors. Finally, we introduce a semi-physical model for the contact resistance to accurately interpret extracted benchmark parameters by means of the transfer length method (TLM). Guidelines to use conventional extraction techniques with special emphasis on TLM are also provided.     

A method for the measurement of the diffusion length and the pn product in silicon

A new method is described for the measurement of the diffusion length and pn product in silicon. The measuring method is based on the measurement of the I-V characteristics of different lateral bipolar transistors fabricated on the same wafer under the same processing conditions. The emitters of these transistors are exactly similar and function only as an injecting boundary to the base regions when they are forward biased. Therefore, the electronic properties of the emitters are irrelevant. The method has been analyzed theoretically and experimentally. The results have been compared with the results of other common measuring methods and good agreement has been obtained. The method is characterized by its simplicity. Also, it has the advantage that the diffusion length and the pn product are determined in the same region of the same device.     

Oxide current in MOS transistors operated under charge pumping conditions

The present paper describes an alternative approach for isolating the oxide current from the gate current (GC) and its use for characterizing the bulk oxide in MOS transistors. The method is based on measurements of the gate as well as the substrate currents of MOS transistors pulsed by a train of square wave pulses under charge pumping conditions.The measurements are done on various experimental devices and different gate and drain/source voltage biasing. The GC has been measured and was found to be of typical behavior when it is plotted with respect to the gate voltage. Moreover, the gate and substrate currents are found to be of complementary shapes when plotted with respect to gate voltage. This behavior is made useful in studying and characterizing the oxide and the interface of MOS transistors.     

晶体管红外热像图的热谱分析方法

使用自编的分析软件，根据比色法对所摄取的晶体管红外热像图进行了热谱分析，给出了晶体管发射区热谱和发射区一维温度分布曲线．一维温度分布曲线给出了整个发射区的结温分布情况，并可直接读取发射区的峰值结温和最低结温，还可以计算出平均结温．晶体管热谱是表示晶体管结温不均匀性的一种与热像图不同的新方法．     

Characterization of polysilicon-gate depletion in MOS structures

This paper presents a new technique to characterize the depletion capacitance and (active) impurity concentration of gate polysilicon in MOS transistors. The method has been validated by means of 2-D simulation; experimental results obtained with state-of-the-art n-channel 0.5 micrometer transistors are presented     

MOS器件中寄生双极型晶体管模型参数的提取

在晶体管GP模型基础上,采用Silvoca公司的UTMOST模型参数提取程序,得到一种双极型晶体管模型参数的提取方法.用此方法对PCM测试芯片的寄生三极管进行参数提取和模拟,模拟结果与测试结果符合得较好.     

A new method for determining the reverse transit time in bipolartransistors

The reverse transmit time is an important parameter for determining the delay of bipolar transistors in saturation. A new method is proposed to extract the reverse transit time of bipolar transistors. The technique is based on AC short-circuit current gain measurements using a network analyzer. The method is very simple and is very useful for on-wafer measurements     

Low frequency conductance voltage analysis of Si/GexSi1-x/Si heterojunction bipolar transistors

Low-frequency-conductance-voltage (LFGV) method for analysis of heterojunction bipolar transistors (HBTs) is presented. The method gives accurate quantitative values for the important minority-carrier transport parameters that underlie the transistor performance, such as the base diffusion length, lifetime, diffusion coefficient and transit time. The method also allows a detailed analysis of the current gain and emitter injection efficiency. The analytical model and experimental methodology are demonstrated for a Si/Ge_xSi_1-x/Si HBT with a trapeziodal and linearly graded Ge profiles in the base. The LFGV method is general and can be applied to other bipolar transistors, including those based on III-V materials     

Electron mobility measurement in short-channel FET's using thecutoff frequency method

The cutoff frequency (FT) method is presented to measure electron mobility in short-channel field-effect transistors (FETs). This technique was used to study the electron mobilities in AlGaAs-GaAs self-aligned heterostructure insulated-gate field-effect transistors (HIGFETs), with both undoped and doped channels (E and D mode). The structures were molecular-beam-epitaxy (MBE) grown on 〈100〉-oriented semi-insulating GaAs substrates. All layers were undoped during the growth. The D-mode HIGFETs were implemented on the same wafer through selective implantation of silicon ions into the channel. Computer simulations indicate that all the channels are in the GaAs layers. The data from the FT method are slightly higher than those from the previously proposed method, owing to the fact that the parasitic capacitance effects have not been excluded in the latter     

漂移区为线性掺杂的高压薄膜SOI器件的研制

给出了漂移区为线性掺杂的高压薄膜SOI器件的设计原理和方法.在Si膜厚度为0.15μm、隐埋氧化层厚度为2μm的SOI硅片上进行了LDMOS晶体管的制作.首次对薄膜SOI功率器件的击穿电压与线性掺杂漂移区的杂质浓度梯度的关系进行了实验研究.通过对漂移区掺杂剂量的优化,所制成的漂移区长度为50μm的LDMOS晶体管呈现了高达612V的击穿电压.     

Two-dimensional analytic modeling of very thin SOI MOSFETs

An analytic solution of the Poisson's equation for MOSFETs on very thin SOI (silicon on insulator) was developed using an infinite series method. The calculation region includes the thin SOI and the gate and buried oxides. The results of this model were found to agree well with a two-dimensional (PISCES) simulation in the subthreshold region and the linear region with small V_DS. This model is used to study the short-channel behavior of very small MOS transistors on thin SOI. It is found that with very thin SOI, short-channel effects are much reduced compared to bulk MOS transistors and depend on the bulk-substrate bias. The model also shows that it is possible to fabricate submicrometer transistors on very thin SOI even if the channel doping is nearly intrinsic