On-chip solid-state cooling for integrated circuits using thin-film microrefrigerators

An overview of recent advances in solid-state cooling utilizing thin-film silicon germanium-based microrefrigerators is given. Key parameters affecting micro cooler performance are described. A 3-/spl mu/m thick 200/spl times/ (3 nm Si/12 nm Si/sub 0.75/Ge/sub 0.25/) superlattice device can achieve maximum cooling of 4/spl deg/C at room temperature, maximum cooling power density of 600 W/cm/sup 2/ for 40-/spl mu/m diameter device and fast transient response on the order of tens of micro-seconds independent of the device size. Three-dimensional electrothermal simulations show that individual microrefrigerators could be used to remove hot spots in silicon chips with minimal increase in the overall power dissipation.     

A comparison of thin film microrefrigerators based on Si/SiGe superlattice and bulk SiGe

Most of the conventional thermal management techniques can be used to cool the whole chip. Since thermal design requirements are mostly driven by the peak temperatures, reducing or eliminating hot spots could alleviate the design requirements for the whole package. Monolithic solid-state microcoolers offer an attractive way to eliminate hot spots. In this paper, we review theoretical and experimental cooling performance of silicon-based microrefrigerators on a chip. Both Si/SiGe superlattice and also bulk SiGe thin film devices have been fabricated and characterized. Direct measurement of the cooling along with material characterization allows us to extract the key factors limiting the performance of these microrefrigerators. Although Si/SiGe superlattice has larger thermoelectric power factor, the maximum cooling of thin film refrigerators based on SiGe alloys are comparable to that of superlattices. This is due to the fact that the superlattice thermal conductivity is larger than bulk SiGe alloy by about 30%.     

LSI multiplier using high speed ULG

The three-gating stage 4/spl times/4-bit multiplier design and its LSI realization using 34 ECL cascode cells are described. Use of a modular single-stage universal logic gate as the primary logic building block in the multiplier allows achievement of a factor of 2 delay reduction relative to multipliers described previously.     

On-chip activation of superlattice detectors via light coupled out laterally from optical fibres

A novel scheme for tapping of signals carried in optical fibres is demonstrated. Lateral holes through the fibre cladding, formed by lithography and chemical etching or laser machining, are filled with a high-index plug to allow access to the guiding region. The fibre is positioned in a groove in the active semiconductor wafer, and the holes are aligned with a row of mesa-type superlattice avalanche photodiodes which detect the optical signal.     

Simultaneous high speed OTDM add-drop multiplexing using GT-UNI switch

The authors describe the excellent capability of an all-optical gain-transparent ultrafast nonlinear interferometer (GT-UNI) in dropping, passing through, and adding optical time domain multiplexing (OTDM) channels. Error free operation without significant penalties of a complete OTDM add-drop node at 80 Gbit/s was achieved.     

On-chip vertical tapered solenoid inductor with high self-resonance frequency

A novel on-chip vertical tapered solenoid inductor has been designed fabricated and experimentally characterised. Owing to its vertical tapered solenoid structure, it is observed that the frequency corresponding to the peak quality factor (f_Qmax) increases by 160%, i.e. from 4.05 to 10.55 GHz, and the self-resonance frequency (f_sr) increases from 21.3 to more than 25 GHz, when compared to a traditional planar inductor of similar inductance and on-chip area. Further, this inductor is found to exhibit a self-shielding characteristic which has a strong impact on the requirements of floating shields underneath the inductor. The performance of the inductor is also characterised at different temperatures.     

Double-sided cooling for high power IGBT modules using flip chiptechnology

A new technique for the packaging of IGBT modules has been developed. The components are sandwiched between two direct bond copper (DBC) substrates with aluminum nitride. Wire bonds are replaced with flip chip solder bumps, which allows cooling of components on both sides. Microchannel heat sinks are directly integrated in the package to decrease the thermal resistance of the module. Thus, a very compact module with high thermal performance is obtained. A prototype with two insulated gate bipolar transistors (IGBTs) and four diodes associated in parallel was realized and tested. In this paper, the innovative packaging technique is described, and results of thermal tests are presented     

On-chip decoupling capacitor optimization using architectural level prediction

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.     

On-board baseband switch development using A high speed optical ring

This paper presents work performed at COMSAT Laboratories to develop a prototype on-board baseband switch. The switch design is modular to accommodate different service types, and the architecture features a high-speed optical ring operating at 1 Gb/s to route input (up-link) channels to output (down-link) channels. The switch is inherently a packet switch, but can process either circuit-switched or packet-switched traffic. If the traffic arrives at the satellite in a circuit-switched mode, the input processor packetizes it and passes it on to the switch. The main advantage of the packet approach lies in its simplified control structure. Details of the switch architecture and design, and the status of its implementation, are presented.     

A high speed GaAs 8-bit multiplexer using capacitor-coupled logic

Capacitor-coupled logic has been used to design and fabricate a GaAs eight channel multiplexer IC for use at 1.2 Gbit/s, which is fully compatible with ECL, and which offers good stability and very high tolerances to device parameters and circuit voltages. A technique has been developed to enable initial charging of all the coupling capacitors, upon application of a simple pulse sequence to control lines. Preliminary results show correct operation of the multiplexer when operated on wafer probes up to 250 MHz, the present practical limit for such measurements. Higher frequency measurements will be carried out on packaged devices, but these results are not yet available. The divide-by-two elements in the multiplexer can be programmed to self oscillate at /SUP 1///SUB 4/ their maximum usable frequency, allowing simple testing of high frequency performance. A very good agreement between the measured maximum usable frequencies and those predicted from the oscillation frequencies has been achieved, with over 60 percent yield for dividers. On the basis of these preliminary results, indicating operation at speeds up to about 600 MHz, it is anticipated that future wafers with 1 /spl mu/m gate lengths will operate at 1.2 Gbits/s.     

On-chip solenoid inductors with high quality factor for high frequency magnetic integrated circuits

On-chip solenoid inductors for high frequency magnetic integrated circuits are proposed. The eddy current loss was reduced by dividing the inductor into three consecutive inductors connected in series. The inductor has an inductance of 1.1nH and the maximum quality factor (Q/sub max/) of 50.5. The self-resonant frequency and the operating frequency at Q/sub max/ are greater than 17.5GHz and 16.7GHz, respectively.     

An energy band-pass filter using superlattice structures

A novel quantum mechanical energy band-pass filter (EBPF) using semiconductor superlattices is proposed. Such structures with a Gaussian superlattice potential profile allow the incident electrons to be nearly totally transmitted when the impinging electron energy is in the passband. On the other hand, a complete reflection occurs when the impinging energy is in the stopband. By adjusting the parameters of the potential profile and the superlattice, the desired passband and stopband of such filter can be obtained. Time evolution of an electron wave packet moving through such a structure is calculated by numerically solving the time-dependent Schrodinger equation. The numerical simulation clearly demonstrates the characteristics of total transmission and total reflection. The generalized concept of matched quantum-mechanical wave impedance (QMWI) analogous to that used in the transmission line theory is presented to explain the occurrence of total transmission of the proposed structures     

Lifting the limits on high speed wireless data access using antennaarrays

The explosive growth of both the wireless industry and the Internet is creating a huge market opportunity for wireless data access. Limited Internet access, at very low speeds, is already available as an enhancement to some existing cellular systems. However, those systems were designed with the purpose of providing voice services and-at most-short messaging, but not fast data transfers. In fact, as shown in this article, traditional wireless technologies are not very well suited to meet the demanding requirements of providing very high data rates with the ubiquity, mobility, and portability characteristic of cellular systems. Increased use of antenna arrays appears to be the only means of enabling the types of data rates and capacities needed for wireless Internet and multimedia services. While the deployment of base station arrays is becoming universal, it is really the simultaneous deployment of base station and terminal arrays that can unleash unprecedented levels of performance by opening up multiple spatial signaling dimensions     

适用于高数据速率和高速移动环境的多相位匹配信道估计方法

本文给出了多相位匹配信道估计方法，通过这种方法，可以有效地将高维的PSK调制的性能改善到低维的PSK性能，使得在高速移动环境中可以应用高维的PSK调制，因而这是一种适用于高数据速率和高速移动环境的一种有效的信道估计方法。     

On-chip high voltage charge pump in standard low voltage CMOS process

An on-chip high voltage tolerant 4VDD charge pump with symmetrical architecture in a standard low voltage 1.8 V 0.18 /spl mu/m CMOS process is presented. For a 250 k/spl Omega/ load, circuit efficiency of the charge pump is approximately 71%. All the MOS transistors satisfy typical voltage stress related reliability requirements for standard low voltage CMOS devices.     

Adaptive equalization for high speed optical MIMO wireless communications using white LED

Light emitting diode (LED) is one of the most important light sources in the 21st century and has broad prospects in the illumination.Currently,the white LED is used not only for illumination,but also ...     

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.     

On-chip ESD protection design by using polysilicon diodes in CMOSprocess

A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is proposed in this paper. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-puIse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original ~300 V to become ⩾3 kV. This design has been practically applied in a mass-production smart-card IC     

使用高速逻辑分析仪探测高速数字系统

在过去几十年中,数字设计人员一直依赖逻辑分析仪,作为系统检验的主要工具。近年来,时钟速率的加快,已经迫使设计人员考虑系统所有部分的信号完整性,包括测试能力。逻辑分析仪探头不再是任意连接到系统上就能够保证成功,而是必须考察探头位置、负荷及与传输线的邻近程度等因素。本文考察了在探测高速数字系统时设计人员遇到的部分常见问题,