From 101 to nnn: a review and a classification of computer game architectures

The game world graph (GWG) framework is a taxonomy for analyzing and classifying computer game architectures. This article presents a systematic review of game architectures using the GWG framework. The review validates the usefulness of the GWG framework through classifying game architectures described in the literature into distinct categories according to the framework. The major contribution of the paper is a state-of-the-art presentation of 40 different game architectures, which covers architectures for all kinds of games from single player games to massively multiplayer online games (MMOGs). Previous reviews of game architectures have focused on a narrower selection of games such as only networked games, MMOGs or similar. Further, none of the previous reviews has used a systematic framework for analyzing the characteristics of game architectures. Using the framework, we can identify similarities and differences of the 40 game architectures in a systematic way. Finally, the paper outlines the evolution of the game architectures from the perspective of the GWG framework.     

Homogeneous and heterogeneous parallel architectures in real-time signal processing and control

This paper presents an investigation into the real-time performance of parallel architectures in signal-processing and control applications. Several algorithms of regular and irregular nature are implemented on a number of architectures. Hardware and software resources, and the capabilities of the architectures and characteristics of the algorithms are considered for suitable matching between the algorithms and the architectures. The partitioning and mapping of the algorithms on the architectures and inter-processor communication techniques are investigated. Finally, a comparison of the results of various implementations is made to establish the merits of the design and development of parallel architectures for real-time signal-processing and control applications.     

制造系统控制结构研究的新进展

制造系统的控制结构是自动化和先进制造领域的重要研究课题.本文从现代制造的需求出发,研究比较了基于Agent的控制和Holon制造模式这两种现代制造系统的主流控制结构的概念、特性、研究成果和主要差别,并介绍了将两者结合的最新研究动态和进展,最后对其发展趋势进行了分析和探讨.     

分布式物流管理系统体系结构研究与探讨

根据当前网络经济不断深化发展、分布式物流管理系统应用越来越广泛的实际情况,分析了基于Mierosott DNA的DCOM/COM 、基于CORBA的RMUEJB、基于XML?和SOAP的Web Services这3种主流的分布式体系结构的特点,比较了这3种分布式体系结构的性能,探讨了如何实现这3种结构间的互操作问题,并结合不同的系统开发目的说明了这些结构的适用范围及与当前一些新技术相结合的方法与途径.     

软件体系结构动态演化的条件超图文法及分析

针对目前.软件体系结构动态演化描述方法的不足,提出用约束超图表示软件体系结构,用左右应用条件刻画软件体系结构动态演化的前断言和后断言,用条件超图文法建模软件体系结构动态演化过程.通过案例分析,讨论了如何构建条件超图文法并应用于软件体系结构动态演化.在此基础上,建立软件体系结构动态演化的一致性条件定义,给出动态演化的一致性判定方法.最后,设计实验进行分析,验证了方法的有效性.     

Multilayered neural architectures evolution for computing sequences of orthogonal polynomials

This article presents an evolutionary algorithm to autonomously construct full-connected multilayered feedforward neural architectures. This algorithm employs grammar-guided genetic programming with a context-free grammar that has been specifically designed to satisfy three important restrictions. First, the sentences that belong to the language produced by the grammar only encode all valid neural architectures. Second, full-connected feedforward neural architectures of any size can be generated. Third, smaller-sized neural architectures are favored to avoid overfitting. The proposed evolutionary neural architectures construction system is applied to compute the terms of the two sequences that define the three-term recurrence relation associated with a sequence of orthogonal polynomials. This application imposes an important constraint: training datasets are always very small. Therefore, an adequate sized neural architecture has to be evolved to achieve satisfactory results, which are presented in terms of accuracy and size of the evolved neural architectures, and convergence speed of the evolutionary process.     

Cross-Layer Architectures for Autonomic Communications

Layered architectures are not flexible enough to cope with the dynamics of wireless dominated next generation communications. Cross-layer architectures may provide a more flexible solution: breaks the traditional structure by allowing interactions between two or more non-adjacent layers. This paper review the cross–layer approach to network architecture and compare the different cross-layering architectures, observing that most current approaches depend purely on local information and provide only poor and inaccurate information gathering at the global scale. This paper also explores the possible use of cross-layering architectures in autonomic communications and the potential importance of new cross-layer architectures with a hybrid local and global view for autonomic communications.     

OpenMP compiler for distributed memory architectures

OpenMP is an emerging industry standard for shared memory architectures. While OpenMP has advantages on its ease of use and incremental programming, message passing is today still the most widely-used programming model for distributed memory architectures. How to effectively extend OpenMP to distributed memory architectures has been a hot spot. This paper proposes an OpenMP system, called KLCoMP, for distributed memory architectures. Based on the partially replicating shared arrays memory model, we propose ...     

Communication Architectures for Massive Multi-Player Games

Massive multi-player games are characterized by a large number of participating players. It is therefore essential that an appropriate communication architecture is deployed in order to support an ever growing number of players. Several such architectures have been proposed, including client-server and peer-to-peer architectures. In this paper, we propose a systematic method to assess the scalability of different architectures in order to identify the most appropriate one for specific game types. The model proposed is very general in that it covers centralized, distributed, and hybrid architectures and it is applied to the client-server, peer-to-peer and the newly introduced federated peer-to-peer architecture. Quantitative expressions that capture the effect of various game types are derived, and the trade-offs among the architectures are identified.     

Recent trends in control architectures for autonomous underwater vehicles

This article describes therecenttrends in controlarchitectures for autonomous vehicles. The study has been carried out on 22 architectures, most of which relate to the field of underwater robotics. The main aim of this article is to show the relationships between these various architectures and to show how developments in architectures for autonomous land vehicles have been extended for use in autonomous underwater vehicles. A summary of important features of the 22 architectures is presented and a new hybrid architecture is proposed for the underwater vehicle GARBI.     

A framework for analysis and design of software reference architectures

Context

A software reference architecture is a generic architecture for a class of systems that is used as a foundation for the design of concrete architectures from this class. The generic nature of reference architectures leads to a less defined architecture design and application contexts, which makes the architecture goal definition and architecture design non-trivial steps, rooted in uncertainty.

Objective

The paper presents a structured and comprehensive study on the congruence between context, goals, and design of software reference architectures. It proposes a tool for the design of congruent reference architectures and for the analysis of the level of congruence of existing reference architectures.

Method

We define a framework for congruent reference architectures. The framework is based on state of the art results from literature and practice. We validate our framework and its quality as analytical tool by applying it for the analysis of 24 reference architectures. The conclusions from our analysis are compared to the opinions of experts on these reference architectures documented in literature and dedicated communication.

Results

Our framework consists of a multi-dimensional classification space and of five types of reference architectures that are formed by combining specific values from the multi-dimensional classification space. Reference architectures that can be classified in one of these types have better chances to become a success. The validation of our framework confirms its quality as a tool for the analysis of the congruence of software reference architectures.

Conclusion

This paper facilitates software architects and scientists in the inception, design, and application of congruent software reference architectures. The application of the tool improves the chance for success of a reference architecture.     

分布式实时系统结构的研究

本文首先介绍了分布式实时系统的应用背景 ,论述了两种传统的分布式实时系统的体系结构 ,重点研究了两种新型结构特征 ,目前采用这种新结构的实时系统还不多 ,但实验证明这两种体系结构很适合分布式实时环境的应用     

Performance analysis of hybrid network multiprocessor architecture

In this paper we investigate architectures that combine message‐passing and shared‐memory technologies, called hereinafter hybrid architectures. We introduced hybrid architectures in which large buses of the shared‐memory are split into a number of small high‐performance shared‐memory blocks, which are connected via message‐passing architecture, such as hypercube, grid or ring. This way we avoid the possible degradation of the achieved performance due to the fact that the bus performance does not scale well when the number of processors it connects increases. We study the saturation situations of several hybrid network architectures, where adding processors does not reduce the overall execution time. We show that the use of hybrid network architectures leads to significant improvement of the systems price/performance ratio, by significantly improving the performance with almost no system cost increment. Therefore, the usage of hybrid architectures demonstrates how minimal ‘cost’ spending could significantly increase the system performance. In addition, we show that different types of applications have different best hybrid architectures. Copyright © 2000 John Wiley & Sons, Ltd.     

Comparative performance evaluation of hot spot contention betweenMIN-based and ring-based shared-memory architectures

Hot spot contention on a network-based shared-memory architecture occurs when a large number of processors try to access a globally shared variable across the network. While multistage interconnection network (MIN) and hierarchical ring (HR) structures are two important bases on which to build large scale shared-memory multiprocessors, the different interconnection networks and cache/memory systems of the two architectures respond very differently to network bottleneck situations. In this paper, we present a comparative performance evaluation of hot spot effects on the MIN-based and HR-based shared-memory architectures. Both nonblocking MIN-based and HR-based architectures are classified, and analytical models are described for understanding network differences and for evaluating hot spot performance on both architectures. The analytical comparisons indicate that HR-based architectures have the potential to handle various contentions caused by hot spots more efficiently than MIN-based architectures. Intensive performance measurements on hot spots have been conducted on the BBN TC2000 (MIN-based) and the KSR1 (HR-based) machines. Performance experiments were also conducted on the practical experience of hot spots with respect to synchronization lock algorithms. The experimental results are consistent with the analytical models, and present practical observations and an evaluation of hot spots on the two types of architectures     

Hyperreconfigurable architectures and the partition into hypercontexts problem

Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increasing flexibility of modern dynamically reconfigurable systems improves their adaptability to computational needs but also makes fast reconfiguration difficult because of the large amount of reconfiguration information which has to be transferred. However, even when a computation uses this flexibility it will not use it all the time. Therefore, we propose to make the potential for reconfiguration itself reconfigurable. Such architectures are called hyperreconfigurable. Different models of hyperreconfigurable architectures are proposed in this paper. We also study a fundamental problem that emerges on such architectures, namely, to determine for a given computation when and how the potential for reconfiguration should be changed during run time so that the reconfiguration overhead is minimal. It is shown that the general problem is NP-hard but fast polynomial time algorithms are given to solve this problem for special types of hyperreconfigurable architectures. We define two example hyperreconfigurable architectures and illustrate the introduced concepts for corresponding application problems.     

A framework to generate domain-specific manycore architectures from dataflow programs

In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures.However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture.We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures.     

Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs

SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis (HLS) is a powerful method to explore different design architectures in FPGAs. In this paper, the HLS tool from Xilinx is used to generate different design architectures and then analyze the probability of errors in those architectures. Two different case studies scenarios are investigated. First, it is evaluated the influence of control flow and pipeline architectures combined with the use of specialized DSP blocks in the FPGA. The number of errors classified as silent data corruption and timeout according to the architectures and DSP blocks usage is analyzed. Moreover, more possibilities of HLS designs are explored such as data organization, aggressive pipeline insertion and the implementation of the algorithm in a soft processor like the Microblaze from Xilinx. These architectures are strongly optimized in performance and the least susceptible design under soft errors is investigated. All case-study designs are evaluated in a 28 nm SRAM-based FPGA under fault injection. The dynamic cross section, soft error rate and mean work between failures are calculated based on the experimental results. The proposed characterization method can be used to guide designers to select better architectures concerning the susceptibility to upsets and performance efficiency.     

串行迭代结构在RS解码器设计中的应用

RS码解码算法中存在着大量的多项式间的运算。本文通过对这些运算进行相应的变换，将其转换成迭代的形式，并提出一种串行迭代结构来完成对变换后的表达式的实现。经FPGA验证表明，应用串行迭代结构实现的RS解码器减少了所需硬件资源，并获得了很好的纠错性能。     

两种客户／服务器DBMS实现及其效率研究

两种客户／服务器ＤＢＭＳ实现及其效率研究冯玉才，金树东，王元珍（华中理工大学计算机科学与工程系，武汉４３００７４）摘要本文介绍在一个多用户ＤＢＭＳ基础上，实现标准客户／服务器ＤＢＭＳ和改进的客户／服务器ＤＢＭＳ的基本结构，其特点是将数据库系统的各层次软件.