A unified approach to RF and microwave noise parameter modeling inbipolar transistors

A unified approach to RF and microwave noise parameter modeling in bipolar transistors is presented. Circuit level noise parameters including the minimum noise figure, the optimum generator admittance, and the noise resistance are analytically linked to the fundamental noise sources and the y-parameters of the transistor through circuit analysis of the chain noisy two-port representation. Comparisons of circuit level noise parameters from different physical models of noise sources in the transistor were made against measurements in UHV/CVD SiGe HBTs. A new model for the collector shot noise is then proposed which produces better noise parameter agreement with measured data than the SPICE noise model and the thermodynamic noise model, the two most recent Y-parameter based noise models     

Noise in SiGe HBT RF Technology: Physics, Modeling, and Circuit Implications

This paper presents an overview of the physics, modeling, and circuit implications of RF broad-band noise, low-frequency noise, and oscillator phase noise in SiGe heterojunction bipolar transistor (HBT) RF technology. The ability to simultaneously achieve high cutoff frequency (f/sub T/), low base resistance (r/sub b/), and high current gain (/spl beta/) using Si processing underlies the low levels of low-frequency 1/f noise, RF noise, and phase noise of SiGe HBTs. We first examine the RF noise sources in SiGe HBTs and the RF noise parameters as a function of SiGe profile design, transistor biasing, sizing, and operating frequency, and then show a low-noise amplifier design example to bridge the gap between device and circuit level understandings. We then examine the low-frequency noise in SiGe HBTs and develop a methodology to determine the highest tolerable low-frequency 1/f noise for a given RF application. The upconversion of 1/f noise, base resistance thermal noise, and shot noises to phase noise is examined using circuit simulations, which show that the phase noise corner frequency in SiGe HBT oscillators is typically much smaller than the 1/f corner frequency measured under dc biasing. The implications of SiGe profile design, transistor sizing, biasing, and technology scaling are examined for all three types of noises.     

Modeling and characterization of SiGe HBT low-frequency noise figures-of-merit for RFIC applications

We present the first systematic experimental and modeling results of noise corner frequency (f/sub C/) and noise corner frequency to cutoff frequency ratio (f/sub C//f/sub T/) for SiGe heterojunction bipolar transistors (HBTs) in a commercial SiGe RF technology. The f/sub C/ and f/sub C//f/sub T/ ratio are investigated as a function of operating collector current density, SiGe profile, breakdown voltage, and transistor geometry. We demonstrate that both the f/sub C/ and f/sub C//f/sub T/ ratio can be significantly reduced by careful SiGe profile optimization. A comparison of the f/sub C/ and f/sub C//f/sub T/ ratio for high breakdown and standard breakdown voltage devices is made. Geometrical scaling data show that the SiGe HBT with A/sub E/=0.5/spl times/2.5 /spl mu/m/sup 2/ has the lowest f/sub C/ and f/sub C//f/sub T/ ratio compared to other device geometries. An f/sub C/ reduction of nearly 50% can be achieved by choosing this device as the unit cell in RF integrated-circuit design.     

Lateral high-speed bipolar transistors on SOI for RF SoC applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.     

RF small signal avalanche for bipolar transistor circuit design: Characterization, modeling and repercussions

In the face of increasing demands for high frequency and high output power of modern bipolar transistor circuits, electronic circuit designers are exploring regimes of transistor operation that meet both requirements and enter RF regimes, where impact ionization is significant. The present paper addresses AC/RF avalanche characterization techniques. Repercussions of avalanche breakdown on some important transistor properties like unilateral power gain and the stability factor are introduced and demonstrated by measurements on modern industrial devices. On the basis of theoretical considerations and compact model simulations it is shown when avalanche can be expected to have significant impact on AC performance of bipolar transistors.     

An alternative method for transistor low frequency noise estimation by measuring phase noise of test oscillator

In this paper we suggest an alternative method for the analysis of low frequency noise of transistors based on measurements of phase noise of a test oscillator. This method is demonstrated by experimental results obtained with a simple test oscillator with HEMT, and central frequency of 13.769 GHz. The main contribution to phase noise of the test oscillator comes from up conversion of transistor LF noise. This idea and the method can be used for the selection of transistors for high frequency application or for design of test circuit in RF IC manufacture.     

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

It has been known that using selective epitaxial growth (SEG) of silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency (f/sub max/) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on DC and RF performance of NMOS transistors. Up to a 28%-45% improvement in f/sub max/ is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain (/sup E/S/D) architecture. The maximum transconductance (g/sub m/) of the /sup E/S/D device reaches a value of 1100 mS/mm, which in turn gives a very high f/sub T/ of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.     

Frequency and bias-dependent modeling of correlated base and collector current RF noise in SiGe HBTs using quasi-static equivalent circuit

This paper presents modeling of correlated RF noise in the intrinsic base and collector currents of SiGe heterojunction bipolar transistors using quasi-static equivalent circuits. The noises are first extracted from measured noise parameters using standard noise circuit analysis. Using the extraction results, model equations are proposed to describe both the frequency and bias dependence of the correlated noise sources using a single set of model parameters. The model is demonstrated using noise data from both measurement and microscopic noise simulation. The model is shown to work at frequencies up to at least half of the peak f/sub T/ and at biasing currents below high injection f/sub T/ rolloff.     

Device and technology evolution for Si-based RF integrated circuits

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.     

Horizontal current bipolar transistor (HCBT) process variations for future RF BiCMOS applications

Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a [110] wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (C/sub BC/) and minimized volume of the extrinsic regions. The effect of doping levels at different regions on the transistor performance is examined in the two process designs. The fabricated HCBTs exhibit cutoff frequencies (f/sub T/) from 19.2 to 25.6 GHz, maximum frequencies of oscillations (f/sub max/) from 32.2 to 39.6 GHz, and collector-emitter breakdown voltages (BV/sub CEO/) between 4 and 5.2 V, which are the highest f/sub T/ and the highest f/sub T//spl middot/BV/sub CEO/ product compared to existing silicon-on-insulator (SOI) lateral bipolar transistors (LBTs). The compact nature of the HCBT structure and low-cost technology make it suitable for integration with advanced pillar-like CMOS and SOI CMOS devices.     

Circuit for monitoring BJT RF performance using DC measurements

A test circuit is described for on-wafer monitoring of high-frequency performance of bipolar junction transistors using only dc measurements. The test circuit includes an oscillation-amplitude detector and a high-frequency (/spl sim/3 GHz) oscillator whose minimum bias current for oscillation I/sub osc/ correlates strongly with the transistors' maximum oscillation frequency f/sub max/. Variations in the circuit's I/sub osc/ can be routinely monitored to track changes in f/sub max/ caused by process variations. Monte Carlo simulations showed a correlation coefficient of -0.79 between I/sub osc/ and f/sub max/. Variations in measured f/sub max/ intentionally introduced through layout variations were verified to be strongly correlated with I/sub osc/.     

Pseudomorphic In/sub 0.52/Al/sub 0.48/As/In/sub 0.7/Ga/sub 0.3/As HEMTs with an ultrahigh f/sub T/ of 562 GHz

We fabricated decananometer-gate pseudomorphic In/sub 0.52/Al/sub 0.48/As/In/sub 0.7/Ga/sub 0.3/As high-electron mobility transistors (HEMTs) with a very short gate-channel distance. We obtained a cutoff frequency f/sub T/ of 562 GHz for a 25-nm-gate HEMT. This f/sub T/ is the highest value ever reported for any transistor. The ultrahigh f/sub T/ of our HEMT can be explained by an enhanced electron velocity under the gate, which was a result of reducing the gate-channel distance.     

Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors

Highly linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported. In MGTR circuitry, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/' of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output for the amplifier and by the tuned load for the mixer. Experimental results designed using the above techniques show IIP/sub 3/ improvements at given power consumption by as much as 10 dB for CMOS low-noise amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and noise figure.     

High-frequency characterization and modeling of distortion behavior of MOSFETs for RF IC design

High frequency (HF) distortion of MOSFETs has been characterized at different frequencies and bias conditions with a single tone measurement system. The results show that a MOSFET has much higher "low frequency limit" (LFL) than a bipolar transistor with similar critical dimensions, implying that the HF distortion characteristics of MOSFETs operating at a frequency lower than LFL is dictated by its low-frequency behavior. This discovery is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. It has also been found that the second harmonic P/sub f2/ reaches to its minimum as f/sub T/ peaks, due to a similar nonlinearity cancellation as in bipolar transistors. Furthermore, the measured data shows fairly constant distortion characteristics over a wide range of drain biases as the device operates in the saturation region. Simulation with a BSIM3v3-based sub-circuit model demonstrates that the distortion behavior of MOSFETs can be well predicted by an RF model if it can accurately describe both dc and ac characteristics with proper parameter extraction. Sensitivity of the distortion on various physical effects, such as the mobility degradation, velocity saturation, channel length modulation, and drain-induced barrier lowering, are also studied to provide insights of the key nonlinearity variation contributors from a practical modeling point of view.     

RFCMOS Unit Width Optimization Technique

In this paper, we demonstrate a unit width ( W_f) optimization technique based on their unity short-circuit current gain frequency (f_T) unilateral power gain frequency (f_MAX)? and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the W_f change is different; hence, some tradeoff is required to obtain the optimum W_f value. During the HF noise analysis, a new FOM is proposed to study the W_f effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in W_f does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistor's layout and helps to select the optimum Wf for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuit's performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum W_f for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies.     

Macromodels in the frequency domain analysis of microwave resonators

This paper describes a 1-V operation Bluetooth RF transceiver in 0.2-/spl mu/m CMOS SOI. The transceiver integrates a radio-frequency transmit/receive switch, an image-reject mixer, a quadrature demodulator, g/sub m/-C filters, an LC-tank voltage-controlled oscillator, a phase-locked loop synthesizer, and a power amplifier. The phase shifter in the quadrature demodulator is tuned dynamically to track the carrier-frequency drift allowed in the Bluetooth specification. The g/sub m/ cell in the filters uses depletion-mode pMOS transistors. In order to achieve 1-V operation, LC-tuned-folded and transistor-current-source-folded circuits are used in the RF and IF building blocks, respectively. In order to minimize power consumption, the current flowing through the circuit is optimally shared between the folded stages. A tuning circuit for the g/sub m/-C filters and a bias generation circuit ensure stable transceiver performance. The transceiver shows -77-dBm sensitivity at 0.1% bit error rate and consumes 33 and 53 mW from 1 V in the transmit and receive modes, respectively.     

Semiconductor devices for RF applications: evolution and current status

This paper reviews the history, evolution, current status, and applications of semiconductor devices for radio frequency (RF) applications. The most important developments and major milestones leading to modern high-performance RF transistors are presented. Heterostructures, which are key elements for some advanced RF transistors, are described, and an overview of the different transistor types and their figures of merit is given. Applications of RF transistors in civil RF systems with special emphasis on wireless communication systems are addressed, and the issues of transistor reliability are also briefly discussed.     

A new HCBT with a partially etched collector

A novel horizontal current bipolar transistor (HCBT), suitable for the integration with the pillar-like MOSFETs, is processed with the reduced volume of the parasitic regions, achieved by the partial etching of the collector n-hill region and the self-protection of the p/sup +/ extrinsic base from tetramethyl ammonium hydroxide etch-back. The HCBT fabricated by a low-cost technology exhibits the cutoff frequency (f/sub T/) of 30.4 GHz, the maximum frequency of oscillations (f/sub max/) of 35GHz and the collector-emitter breakdown voltage (BV/sub CEO/) of 4.2 V, which are the highest f/sub T/ and the highest f/sub T/BV/sub CEO/ product among the lateral bipolar transistors (LBTs).     

A low-power highly linear cascoded multiple-gated transistor CMOS RF amplifier with 10 dB IP3 improvement

A low-power highly linear CMOS RF amplifier circuit composed of a Multiple-Gated common-source FET TRansistor (MGTR) in cascode configuration is reported. In a MGTR amplifier, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/" of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output. IP3 improvement as large as 10 dB has been obtained from an experimental RF amplifier designed at 900 MHz and fabricated using 0.35 /spl mu/m BiCMOS technology using only CMOS at a similar power consumption and gain as those obtainable from conventional cascode single gate transistor amplifiers.     

Fabrication and characterization of 100-nm In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As double-gate HEMTs with two separate gate controls

In this letter, we demonstrate successful operation of 100-nm T-gates double-gate high electron mobility transistors with two separate gate controls (V/sub g1s/ /spl ne/ V/sub g2s/). These devices are fabricated by means of adhesive bonding technique using enzocyclocbutene polymer. The additional gate enables the variation of the threshold voltage V/sub th/ in a wide range from -0.68 to -0.12V while keeping high cutoff frequency f/sub t/ of about 170 GHz and high maximum oscillation frequency f/sub max/ of about 200 GHz. These devices are considered as being very effective for millimeter-wave mixing applications and are promising devices for the fabrication of velocity modulation transistor (VMT) (Sakaki et al., 1982).