A Wide Tuning Range Voltage Controlled Oscillator with a High Tunable Active Inductor

This paper presents a wide tuning range CMOS voltage controlled oscillator (VCO) with a high-tunable active inductor circuit. In this VCO circuit, the coarse frequency is achieved by tuning the integrated active inductor circuit. The VCO circuit is designed in 0.18  \(\upmu \hbox {m}\) CMOS process and simulated with Cadence Spectra. The simulation results show the frequency tuning range from 120 MHz to 2 GHz resulting in a tuning range of 94 %. The phase noise variation is from \(-\) 80 to \(-\) 90 dBc/Hz at a 1 MHz frequency offset, and output power variation is from \(-\) 4.7 to \(+\) 11.5 dBm. The active inductor power consumption is 2.2 mW and the total power dissipation is 7 mW from a 1.8 V DC power supply. By comparing the proposed VCO circuit with the general VCO topology, the results show that this VCO architecture by using the novel, high-tunable and low power active inductor circuit, presents a better performance regarding low chip size, low power consumption, high tuning range and high output power.     

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low-storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with additional logic to achieve the TCAM functionality? This paper proposes an efficient memory architecture, called E-TCAM, which emulates the TCAM functionality with SRAM. E-TCAM logically divides the classical TCAM table along columns and rows into hybrid TCAM subtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced. An example design of \(512\times 36\) of E-TCAM has been successfully implemented on Xilinx Virtex- \(5\) , Virtex- \(6\) , and Virtex- \(7\) field-programmable gate arrays (FPGAs). FPGA implementation results show that E-TCAM obtains \(33.33\)  % reduction in block-RAMs, \(71.07\)  % in slice registers, \(77.16\)  % in lookup tables, \(53.54\)  % in energy/bit/search, and offers \(63.03\)  % improvement in speed, compared with the best available SRAM-based TCAM designs.     

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-\Updelta\Upsigma ADC with 1.5 cycle quantizer delay and improved STF

A 1 GS/s continuous-time delta-sigma modulator (CT- $\Updelta\Upsigma$ M) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- $\Updelta\Upsigma$ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- $\Updelta\Upsigma$ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

Efficient Reverse Converters for 4-Moduli Sets {2^{2n-1}-1, 2^{n}, 2^{n}+1, 2^{n}-1} and {2^{2n-1}, 2^{2n-1}-1, 2^{n}+1, 2^{n}-1} Based on CRTs Algorithm

Speed and complexity of a reverse converter are two important factors that affect the performance of a residue number system. In this paper, two efficient reverse converters are proposed for the 4-moduli sets {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } and {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } with 5 \(n\) -bit and 6 \(n\) -bit dynamic range, respectively. The proposed reverse converter for moduli set {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed based on CRT and New CRT-I algorithms and in two-level structure. Also, an efficient reverse converter for moduli set {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed by applying New CRT-I algorithm. The proposed reverse converters are based on adders and hence can be simply implemented by VLSI circuit technology. The proposed reverse converters offer less delay and hardware cost when compared with the recently introduced reverse converters for the moduli sets {2 \(^{n}+1\) , 2 \(^{n}-1\) ,2 \(^{n}\) , 2 \(^{2n+1}-1\) } and {2 \(^{n}+1\) , 2 \(^{n}-1\) , 2 \(^{2n}\) , 2 \(^{2n+1}-1\) }.     

Six Order Cascaded Power Line Notch Filter for ECG Detection Systems with Noise Shaping

This paper presents the design of an operational transconductance amplifier-C (OTA-C) notch filter for a portable Electrocardiogram (ECG) detection system. A six order cascaded filter is utilized to reduce the effect of the power line interference at (50/60 Hz). The proposed filter is based on a programmable balanced OTA circuit. Based on this, PSPICE post layout simulation results for the extracted filter using 0.25  \(\upmu \) m technology and operating under \(\pm \) 0.8 V voltage supply are also given. The six order notch filter provides a notch depth of 65 dB (43 dB for 4th order), input referred noise spectral density with noise shaping of 9  \(\upmu \) Vrms/ \(\surd \) Hz at the pass band frequencies and 9 mVrms/ \(\surd \) Hz at the notch (zero) frequency which provide noise shaping for the ECG signal. These results demonstrate the ability of the filter to be used for ECG signal filtering which is located within 150 Hz.     

A Novel 2.5–3.1 GHz Wide-Band Low-Noise Amplifier in 0.18 \upmu \hbox {m} CMOS

Aiming for the simultaneous realization of constant gain, accurate input and output impedance matching and minimum noise figure (NF) over a wide frequency range, the circuit topology and detailed design of wide broadband low noise amplifier (LNA) are presented in this paper. A novel 2.5–3.1 GHz wide-band LNA with unique characteristics has been presented. Its design and layout are done by TSMC 0.18  \(\upmu \hbox {m}\) technology. Common gate stage has been used to improve input matching. In order to enhance output matching and reduce the noise as well, a buffer stage is utilized. Mid-stages which tend to improve the gain and reverse isolation are exploited. The proposed LNA achieves a power gain of 15.9 dB, a NF of 3.5 dB with an input return loss less than \(-\) 11.6, output return loss of \(-\) 19.2 to \(-\) 19 and reverse isolation of \(-\) 38 dB. The LNA consumes 54.6 mW under a supply voltage of 2 V while having some acceptable characteristics.     

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low ( \(\sim \) 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage \(V_\mathrm{L}\) ( \(\sim \) 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/ \(V_\mathrm{DD})^{ 2 }\,\times \) 100 %) due to reduced voltage swing (from \(V_\mathrm{DD }\)  = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a \(256 \times 64\) bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.     

A 5 GHZ CMOS Power VCO with Novel Frequency-Modulation for RF Transmitter

A 5 GHz transformer-feedback power oscillator with novel frequency modulation (FM) up to 10 MHz is presented in this paper. The novel FM is achieved by a CMOS transistor between transformer and ground, which is designed for varying the equivalent inductance and mutual inductance of the transformer and shows no DC connection with the oscillation circuit. The major frequency tuning is realized by the variable capacitor which is controlled by a phase lock loop. The RF VCO with 210 MHz tuning range operates in class-E mode to achieve a cost-effective transmitter, which demonstrates a high DC-to-RF conversion efficiency of 39 %. A RF power of 15.1 dBm and phase noise better than \(-\) 109 dBc/Hz @ 100 kHz from the central frequency of 5.5 GHz is obtained with the biasing conditions V \(_\mathrm{ds}\) = 1.8 V and V \(_\mathrm{gs}\) = 0.65 V. The VCO also demonstrates an ultra-low voltage operation capability: with V \(_\mathrm{ds}\) = V \(_\mathrm{gs}\) = 0.6 V and DC power consumption of 9 mW, the output power is 4.5 dBm and the phase noise better than \(-\) 93 dBc/Hz @ 100 kHz. The die size of the transformer-feedback power oscillator is only \(0.4\times 0.6\) mm \(^{2}\) .     

Parametric Analysis of a Novel Architecture of Phase Locked Loop for Communication System

The work proposed parametric analysis of a novel architecture of phase locked loop (PLL) for pure signal synthesis. It has been widely used in wireless communication systems due to the high frequency resolution and the short locking time. First, we presented a mathematical and accurate model of noise in PLL with take into account noise of its component. Then we predicted output phase noise in term of its parameters. Finally, we described as effective technique for noise in fractional PLL by CppSim simulator. The output phase noise has been reduced from \(-154\) to \(-159\,\) dBc/MHz at 20 MHz offset. The proposed behavioral simulation results show improvement around 5 dBc/MHz. In future, this technique can also be implemented in hybrid PLL.     

Low Voltage Low Cost Quadrature Oscillator Based on Active Inductor

This paper presents a new low voltage low cost quadrature oscillator, which consists of two LC negative oscillators based on active inductor. In this quadrature oscillator, the back-gates of the core transistors are used as coupling terminals to provide the quadrature outputs. The proposed floating active inductor has a two layer transistor structure. The quadrature oscillator has been implemented with the chart 0.18  \(\upmu \) m CMOS technology. At the supply voltage of 1.2 V, the total power consumption is 16 mW. The phase noise at 1 MHz frequency offset is \(-\) 111.8 dBc/Hz at the oscillation frequency of 3.946 Hz.     

Anisotropic Thermopower of the Kondo Insulator \hbox {CeRu}_4\hbox {Sn}_6

The intermetallic compound \(\hbox {CeRu}_4\hbox {Sn}_6\) has been tentatively classified as Kondo insulator. This class of material, especially non-cubic representatives, is not yet fully understood. Here we report thermopower measurements on single-crystalline \(\hbox {CeRu}_4\hbox {Sn}_6\) between 2 K and 650 K, along the main crystallographic directions. Large positive thermopower is observed in the directions along which the hybridization is strong and a Kondo insulating gap forms. A negative contribution to the thermopower dominates for the crystallographic \(c\) axis where hybridization is weak and metallicity prevails.     

Method for Designing Efficient Mixed Radix Multipliers

The multiplication of two signed inputs, \(A {\times } B\) , can be accelerated by using the iterative Booth algorithm. Although high radix multipliers require summing a smaller number of partial products, and consume less power, its performance is restricted by the generation of the required hard multiples of B ( \(\pm \phi B\) terms). Mixed radix architectures are presented herein as a method to exploit the use of several radices. In order to implement efficient multipliers, we propose to overlap the computation of the \(\pm \phi B\) terms for higher radices with the addition of the partial products associated to lower radices. Two approaches are presented which have different advantages, namely a combinatory design and a synchronous design. The best solutions for the combinatory mixed radix multiplier for \(64\times 64\) bits require \(8.78\) and \(6.55~\%\) less area and delay in comparison to its counterpart radix-4 multiplier, whereas the synchronous solution for \(64\times 64\) bits is almost \(4{\times }\) smaller in comparison with the combinatory solution, although at the cost of about \(5.3{\times }\) slowdown. Moreover, we propose to extend this technique to further improve the multipliers for residue number systems. Experimental results demonstrate that best proposed modulo \(2^{n}{-}1\) and \(2^{n}{+}1\) multiplier designs for the same width, \(64{\times }64\) bits, provide an Area-Delay-Product similar for the case of the combinatory approach and \(20~\%\) reduction for the synchronous design, when compared to their respective counterpart radix-4 solutions.     

Construction of (2k,k, 2) Convolutional Codes with Double-Loop Cyclic Codes

In this paper, by taking multiple-time information in blocks into the coding of linear block codes, a new class of (2 \(k\) , \(k\) , 2) convolutional codes is constructed, by which a new way of constructing long codes with short ones is obtained. After that, the type of embedded codes is determined and the optimal values of the linear combination coefficients are derived by using a three-dimensional state transfer matrix to analyze and testify the constructing mechanism of the codes. Finally, the simulation experiment tests the error-correcting performance of the (2 \(k\) , \(k\) , 2) convolutional codes for different value of \(k\) , it is shown that the performance of the new convolutional codes compares favorably with that of traditional (2, 1, \(l\) ) convolutional codes.     

A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 \mu m CMOS

A fully integrated low-power, low-complexity ultra wideband (UWB) 3–10 GHz receiver front-end in standard 130 nm CMOS technology is proposed for UWB radar sensing applications. The receiver front-end consists of a full UWB band low-noise amplifier and an on-chip diplexer. The on-chip diplexer has a 1 dB insertion loss and provides a \(-\) 30 dB isolation. The diplexer switch was co-designed with the receiver input matching network to optimize the power matching while simultaneously achieving good noise matching performance. The receiver low-noise amplifier provides a 3–10 GHz bandwidth input matching and a power gain of 17 dB. The overall receiver front-end consumes an average power of 13 mW. The core area of the transceiver circuit is 500 \(\mu \) m by 700 \(\mu \) m.     

A microphone readout interface with 74-dB SNDR

A continuous-time (CT) sigma-delta modulator (SDM) for condenser microphone readout interfaces is presented in this paper. The CT SDM can accommodate a single-ended input and has high input impedance, so that it can be directly driven by a single-ended condenser microphone. A current-sensing boosted OTA-C integrator with capacitive feedforward compensation is employed in the CT SDM to achieve high input impedance and high linearity with low power consumption. Fabricated in a \(0.35\) - \(\upmu\) m complementary metal-oxide-semiconductor (CMOS) process, a circuit prototype of the CT SDM achieves a peak signal-to-noise-and-distortion ratio of 74.2 dB, with 10-kHz bandwidth and \(801\) - \(\upmu\) W power consumption.     

A High Gain,Low-Power Low-Noise Amplifier for Ultra-Wideband Wireless Systems

This paper presents a high gain, low-power common-gate ultra-wideband low-noise amplifier employing a simple configuration for wideband input matching. In our design, a series resistance-inductance network at the source combines with the parasitic capacitance of a transistor to form a parallel RLC input matching configuration in the common-gate input stage. Because of the additional resistance, this matching configuration partially alleviates the restriction of transconductance of the input transistor and also provides wideband matching. The low-noise amplifier was fabricated using the TSMC 0.18  \(\mu \) m technology with an average noise figure of 3.75 dB, a power gain of 18.68 dB with a ripple of \(\pm \)  0.8 dB, an input return loss less than \(-10\)  dB from 3 to 7.6 GHz, and DC power consumption of 8.56 mW, including the output buffer with a 1.8 V supply voltage.     

Delay-dependent robust H_\infty control for 2-D discrete nonlinear systems with state delays

This paper investigates the problem of robust \(H_\infty \) control for a class of 2-D (two-dimensional) discrete state delayed systems with sector nonlinearity described by a model of Roesser type. Firstly, a delay-dependent sufficient condition of robust exponential stability for such 2-D discrete systems is derived in linear matrix inequalities (LMIs) form. Secondly, a delay-dependent exponential stability criterion with \(H_\infty \) performance for the considered systems is also proposed. Then a state feedback \(H_\infty \) controller is constructed based on the above results. Finally, numerical examples are given to illustrate the effectiveness of the proposed method.     

Downlink SINR Study in Multiuser Large Scale Antenna Systems

In this paper, the downlink signal-to-interference-plus-noise ratio (SINR) performance in multiuser large scale antenna systems with matched filter (MF) and regularized zero-forcing (RZF) precoding is investigated. The probability density function (PDF) for MF is derived and the distribution in high signal-to-noise ratio (SNR) regime is studied. Results indicate that the PDF of downlink SINR for MF converges to \(\mathcal F\) distribution when the interference is dominant over noise. For MF, the asymptotic SINR is just the reciprocal of the ratio of the number of users \(U\) to the number of transmit antennas \(N\) , and is irrelevant to the average transmit power when \(N\) and \(U\) grow with fixed ratio. However, when \(U\) is a large constant, the transmit power could be proportional to \(\ln N \big /N \) to maintain a specified quality of service, as a result of the large scale antenna system effect. In addition, the closed form of asymptotic SINR for RZF is derived by solving two mathematical expectations related to eigenvalues of large dimensional random matrices. Simulation results validate the derived PDF and analytical results.     

Novel Tight Closed-Form Bounds for the Symbol Error Rate of EGC and MRC Diversity Receivers Employing Linear Modulations Over \alpha -\mu Fading

In this paper, we propose novel lower and upper bounds on the average symbol error rate (SER) of the dual-branch maximal-ratio combining and equal-gain combining diversity receivers assuming independent branches. \(M\) -ary pulse amplitude modulation and \(M\) -ary phase shift keying schemes are employed and operation over the \(\alpha -\mu \) fading channel is assumed. The proposed bounds are given in closed form and are very simple to calculate as they are composed of a double finite summation of basic functions that are readily available in the commercial software packages. Furthermore, the proposed bounds are valid for any combination of the parameters \(\alpha \) and \(\mu \) as well as \(M\) . Numerical results presented show that the proposed bounds are very tight when compared to the exact SER obtained via performing the exact integrations numerically making them an attractive much simpler alternative for SER evaluation studies.