A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

A 1 V power amplifier for 81–86 GHz E-band

The design and layout of a two stage SiGe E-band power amplifier using a stacked transformer for output power combination is presented. In EM-simulations with ADS Momentum, at E-band frequencies, the power combiner consisting of two individual single turn transformers performs significantly better than a single 2:1 transformer with two turns on the secondary side. Imbalances in the stacked transformer structure are reduced with tuning capacitors for maximum gain and output power. At 84 GHz the simulated loss of the stacked transformer is as low as 1.35 dB, superseding the performance of an also presented alternative power combiner. The power combination allows for a low supply voltage of 1 V, which is beneficial since the supply can then be shared between the power amplifier and the transceiver, thereby eliminating the need of a separate voltage regulator. To improve the gain of the two-stage amplifier it employs a capacitive cross-coupling technique not yet seen in mm-wave SiGe PAs. Capacitive cross-coupling is an effective technique for gain enhancement but is also sensitive to process variations as shown by Monte Carlo simulations. To mitigate this two alternative designs are presented with the cross coupling capacitors implemented either with diode coupled transistors or with varactors. The PA is designed in a SiGe process with f _T  = 200 GHz and achieves a power gain of 12 dB, a saturated output power of 16 dBm and a 14 % peak PAE. Excluding decoupling capacitors it occupies a die area of 0.034 mm².     

A compact 1–30 μH, 1–350 μF, 5–50 mΩ ESR compliant, 1.5% accurate 0.6 μm CMOS differential ΣΔ boost dc–dc converter

Emerging high-end portable electronics demand on-chip integration of high-performance dc–dc power supplies not only to save pin count, printed circuit board (PCB) real estate, and the cost of off-chip components but also to better regulate the point of load (PoL). In the face of a widely variable LC filter, however, integrating the frequency-compensation circuit is difficult without sacrificing stability performance, which is why integrated controller ICs only cater to relatively narrow LC ranges. While ΣΔ control addresses this LC compliance issue in buck dc–dc converters with high equivalent series resistance (ESR) output capacitors, it is not clear how it applies to ΣΔ boost converters. To that end, this paper discusses, analyzes, and experimentally evaluates a prototyped 0.6 μm CMOS differential ΣΔ boost converter. Experimental results verified the switching supply was stable across 1–30 μH, 1–350 μF, and 5–50 mΩ of inductance, capacitance, and ESR while keeping output voltage variations in response to 0.1–0.8 A load and 2.7–4.2 V line changes to less than ±1.5%, peak efficiency at 95%, and switching frequency variation to less than 27%.     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS

A resolution configurable ultra-low power SAR ADC in 0.18 μm CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 × 280 μm².     

System simulations of a 1.5 V SiGe 81–86 GHz E-band transmitter

This paper presents simulation results for a sliding-IF SiGe E-band transmitter circuit for the 81–86 GHz E-band. The circuit was designed in a SiGe process with f _T  = 200 GHz and uses a supply of 1.5 V. The low supply voltage eliminates the need for a dedicated transmitter voltage regulator. The carrier generation is based on a 28 GHz quadrature voltage oscillator (QVCO). Upconversion to 84 GHz is performed by first mixing with the QVCO signals, converting the signal from baseband to 28 GHz, and then mixing it with the 56 GHz QVCO second harmonic, present at the emitter nodes of the QVCO core devices. The second mixer is connected to a three-stage power amplifier utilizing capacitive cross-coupling to increase the gain, providing a saturated output power of +14 dBm with a 1 dB output compression point of +11 dBm. E-band radio links using higher order modulation, e.g. 64 QAM, are sensitive to I/Q phase errors. The presented design is based on a 28 GHz QVCO, the lower frequency reducing the phase error due to mismatch in active and passive devices. The I/Q mismatch can be further reduced by adjusting varactors connected to each QVCO output. The analog performance of the transmitter is based on ADS Momentum models of all inductors and transformers, and layout parasitic extracted views of the active parts. For the simulations with a 16 QAM modulated baseband input signal, however, the Momentum models were replaced with lumped equivalent models to ease simulator convergence. Constellation diagrams and error vector magnitude (EVM) were calculated in MATLAB using data from transient simulations. The EVM dependency on QVCO phase noise, I/Q imbalance and PA compression has been analyzed. For an average output power of 7.5 dBm, the design achieves 7.2% EVM for a 16 QAM signal with 1 GHz bandwidth. The current consumption of the transmitter, including the PA, equals 131 mA from a 1.5 V supply.     

A Miniaturized Monolithic 18–40 GHz Sub-harmonic Mixer

In this paper, a miniaturized 18–40 GHz sub-harmonic mixer is designed and implemented with 0.15 μm GaAs pHEMT process. The proposed mixer employs anti-parallel diode pair with parallel to ground configuration, and a novel coupler structure to feed RF and LO signals, resulting in broadband performance and compact chip size. The measured conversion loss is 10.3–13.5 dB in a wide operation frequency band of 18–40 GHz. The chip size is 0.66 mm².     

A 0.5–1 GHz single stage linear-in-decibel VGA with 80 dB gain range in 0.18 μm CMOS

Communication systems require a wide gain range. For example the code-division multiple access system (CDMA) requires more than 80 dB of gain range so that, many variable gain amplifiers (VGAs) must be used, resulting in high power consumption and low linearity because of VGA non-linearity factors. In this paper, a one-stage VGA in 0.18 μm technology is presented. The VGA based on the class AB power amplifier is designed and simulated for a high linearity and an 80 dB tuning range. For the linear-in-decibel tuning range, transistors in sub-threshold region is used. The current control circuit of the VGA changes gain continuously from ?68 to 18 dB at 0.5 GHz and ?60 to 20 dB at 1 GHz with gain error of less than 2 dB. The power consumption enjoys a highest value about 13.5 mW in the maximum gain and P1dB is also about ?3.4 dBm at 0.5 GHz and 2.2 dBm at 1 GHz.     

A 0.4–3.3 GHz low-noise variable gain amplifier with 35 dB tuning range, 4.9 dB NF,and 40 dBm IIP2

This work presents a low-noise variable gain amplifier (LNVGA) in which the IIP2 is very high, and the gain control is applied to improve the system dynamic range, even with the limitations of the CMOS technology. Two stages compose the LNVGA, a low-noise amplifier, that keeps the noise figure (NF) at low values, and a variable voltage attenuator (VVA), that provides the gain variation. We have applied on the VVA the phase cancellation technique, in which the addition of two out-of-phase signals controls the gain. This technique provides a large gain tuning range only if the paths of the two signalsto be added are well balanced; hence, a precise 180 degrees phase difference is required. In this desing we propose an active balun with small imbalance, which creates those signals. The LNVGA was implemented in 130 nm CMOS with a 1.2 V supply. The measurement results show a 35 dB gain tuning range, varying from 10 to ? 25 dB, a 4.9 dB minimum NF, a ? 10 dBm IIP3, and an IIP2 as high as + 40 dBm.     

An integrated 0.38–6 GHz, 9–12 GHz fully differential fractional-N frequency synthesizer for multi-standard reconfigurable MIMO communication application

A wide-band fully differential fractional-N frequency synthesizer for multi-standard application is presented. The single fully differential LC–VCO with 28.5 % tuning rang and a set of dividers, quadrature self-mixer are designed to accomplish the multi-frequency bands with the frequency band from 0.38 to 6 GHz and from 9.0 to 12 GHz. It covers several wireless standards. A novel high isolation multiplexer is presented to achieve the frequency band selection. This chip was implemented with 65 nm CMOS technology and the maximum consumption is 20.05 mA from 1.2 V power supply. It occupies an active area of 1.5 mm². The measured typical phase noise of the frequency synthesizer is ?114.6 dBc/Hz from 1 MHz offset for 4.85 GHz output.     

A 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction technique

In this Letter, 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 ps_rms at 1.5 GHz operation, and 3.991 ps_rms at 400 MHz operation. The ADPLL occupies 0.088 mm², and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.     

基于 GSVD 的分布式 MIMO 雷达测向算法

针对分布式多输入多输出（multi-input multi-output, MIMO）雷达测向中存在的数据信息提取不充分、运算量偏大等问题，开展了基于广义奇异值分解（generalized singular value decomposition, GSVD）的测向算法研究，以提高低信噪比条件下的角度估计性能。首先，建立了分布式阵列MIMO雷达回波信号的统一化表征模型；其次，将分布式MIMO雷达系统接收阵列数据的多线程GSVD问题转换为一个联合优化问题，运用交替最小二乘（alternating least squares, ALS）技术实现阵列信号流行矩阵的拟合，并引入子空间类算法实现目标角度联合估计；最后，对优化问题增加l1范数约束，避免了每次迭代中进行的奇异值分解运算，降低了算法运算量。仿真实验从角度联合估计、均方误差、运算时间等方面验证了所提算法的有效性。     

A 5.2 mW 240–550 MHz continuous-time low-pass filter and VGA for a UWB receiver in 0.18 μm CMOS process

A very low-power wide-band CMOS continuous-time low-pass filter for a ultra wideband system receiver in 0.18-μm CMOS technology is proposed. The cutoff frequency of the fourth-order LPF can be tuned within 240–550 MHz. The gain of the filter is tuned about 44 dB which can omit the variable gain amplifier (VGA) block. An IIP3 of 17.4 dBm is achieved for a power consumption of 5.2 mW from a 1.8 V power supply. Merging LPF and VGA into one block can efficiently reduce the power consumption and the chip area of the analog baseband channel while achieving a high linearity.     

0.5 V bulk-driven ring amplifier based on master–slave technique

This paper presents a new non-clocked standalone bulk-driven ring amplifier based on master–slave technique that ensures stable operation under process, supply voltage and temperature variations. Unlike the conventional ring amplifier the proposed topology operates without the switched capacitor technique under extremely low supply voltage. The bulk-driven ring amplifier was designed using a triple-well 0.18 µm CMOS technology. The simulation results show a 91 dB gain with 13 μW power dissipation from a 0.5 V supply voltage and the total harmonic distortion was equal to 0.29 %.     

Current-Mode Universal Biquadratic Filter with Five Inputs and Two Outputs Using Two Multi-Output CCIIs

A current-mode universal biquadratic filter with five input terminals and two output terminals is presented. The proposed circuit uses two multi-output second generation current conveyors, two grounded capacitors and three resistors. The new circuit offers the following advantages: use of the minimum number of active components, orthogonal controllability of resonance angular frequency and quality factor, use of grounded capacitors and the versatility to synthesize any type of active filter transfer functions.     

A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

This paper presents the design and Silicon verification of a 2.488–11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. A system modeling approach is described, which is used for optimizing the architectural trade-offs. The transceiver makes use of a low-jitter LC phase locked loop to enable high-reliability system design. The design has 420 fs RJ_rms and consumes 30.1 mW/Gbps at 11.2 Gbps.     

A 4.6 GHz cascade switched biasing LC–QVCO using source-body resistor

This paper presents a 4.6 GHz LC quadrature voltage-controlled oscillator (QVCO) in which the phase noise performance is improved by two methods: cascade switched biasing (CSB) technique and source-body resistor. The CSB topology can reduce the resonator loss caused by MOSFET resistance. Meanwhile, it can maintain the benefits of conventional switched biasing technique. The source-body resistors are utilized to reduce the noise contribution of the substrate related to the cross coupled MOSFETs. The proposed QVCO has been implemented in standard 0.18 μm CMOS technology. With the two methods mentioned above, it consumes 4.9 mW under 1 V voltage supply and achieves a phase noise of ?120.3 dBc/Hz at 1 MHz frequency offset from the carrier of 4.56 GHz. The figure of merit is 186.5 dBc/Hz and the tuning range is from 4.2 G to 5 GHz (17.3 %). When the QVCO operates at 0.8 V voltage supply, the power consumption is 2.88 mW and the phase noise is ?115.7 dBc/Hz at 1 MHz frequency offset from the carrier of 4.58 GHz.     

CMOS CCII– based on modified dual output-OTA for high frequency applications

A negative CMOS second generation current conveyor (CMOS CCII–) based on modified dual output CMOS folded cascode operational transconductance amplifier (CMOS DO-OTA) is presented. The proposed folded cascode CMOS DO-OTA with attractive features for high frequency operation such as high output impedance, wide bandwidth, high slew rate, with low power consumption is used in the realisation. The proposed CMOS DO-OTA and CMOS CCII– with high performance parameters can be used in many high frequency applications. The proposed CMOS CCII– achieves 1.37 GHz (?3 dB BW), 1.8 ns settling time, 48 V/μs slew rate, and low power consumption around 3.25 mW for ±2.5 V supply. P-Spice simulation results are included for 0.5 μm MIETEC CMOS technology.     

An Analysis of the Blockcipher-Based Hash Functions from PGV

Preneel, Govaerts, and Vandewalle (1993) considered the 64 most basic ways to construct a hash function $H{:\;\:}\{0,1\}^{*}\rightarrow \{0,1\}^{n}Preneel, Govaerts, and Vandewalle (1993) considered the 64 most basic ways to construct a hash function H:   {0,1}^*? {0,1}ⁿH{:\;\:}\{0,1\}^{*}\rightarrow \{0,1\}^{n} from a blockcipher E:   {0,1}ⁿ×{0,1}ⁿ? {0,1}ⁿE{:\;\:}\{0,1\}^{n}\times \{0,1\}^{n}\rightarrow \{0,1\}^{n}. They regarded 12 of these 64 schemes as secure, though no proofs or formal claims were given. Here we provide a proof-based treatment of the PGV schemes. We show that, in the ideal-cipher model, the 12 schemes considered secure by PGV really are secure: we give tight upper and lower bounds on their collision resistance. Furthermore, by stepping outside of the Merkle–Damg?rd approach to analysis, we show that an additional 8 of the PGV schemes are just as collision resistant (up to a constant). Nonetheless, we are able to differentiate among the 20 collision-resistant schemes by considering their preimage resistance: only the 12 initial schemes enjoy optimal preimage resistance. Our work demonstrates that proving ideal-cipher-model bounds is a feasible and useful step for understanding the security of blockcipher-based hash-function constructions.