A high efficiency 4-output single inductor DC–DC buck converter with self boosted snubber

This paper presents a single-inductor 4-outputs DC–DC buck converter. In order to independently regulate the four output voltages, a multiple control loop operates on linear combinations of the output voltage errors. An original self-boosted snubber circuit enables load power switches control signals boosting without area and power efficiency penalties. The circuit, fabricated using a 0.5-μm CMOS process, provides four output voltages that can be independently regulated from 0 V to the used supply voltage −500 mV. The supply voltage can range from 2.3 up to 5 V. The overall minimum and maximum output currents are 0.15 and 1.8 A, respectively. The measured maximum cross regulation is 40 mV/V with a peak of power efficiency equal to 85%.     

A soft-switching coupled inductor bidirectional DC–DC converter with high-conversion ratio

A soft-switching bidirectional DC–DC converter is presented herein as a way to improve the conversion efficiency of a photovoltaic (PV) system. Adoption of coupled inductors enables the presented converter not only to provide a high-conversion ratio but also to suppress the transient surge voltage via the release of the energy stored in leakage flux of the coupled inductors, and the cost can kept down consequently. A combined use of a switching mechanism and an auxiliary resonant branch enables the converter to successfully perform zero-voltage switching operations on the main switches and improves the efficiency accordingly. It was testified by experiments that our proposed converter works relatively efficiently in full-load working range. Additionally, the framework of the converter intended for testifying has high-conversion ratio. The results of a test, where a generating system using PV module array coupled with batteries as energy storage device was used as the low-voltage input side, and DC link was used as high-voltage side, demonstrated our proposed converter framework with high-conversion ratio on both high-voltage and low-voltage sides.     

A DC–DC buck converter with load-regulation improvement using dual-path-feedback techniques

A DC–DC buck converter using dual-path-feedback techniques is proposed in this paper. The proposed converter is fabricated with TSMC 0.35 μm DPQM CMOS process. The structure of the proposed buck converter includes the voltage-feedback and current-feedback design to improve load regulation and achieve high efficiency. The experimental results show the maximum power efficiency is about 94 %. The load regulation is 6.22 (ppm/mA) when the load current changes from 0 to 300 mA. With a 3.6 V input power supply, the proposed buck converter provides an adjustable power output with a voltage range is from 1 to 3 V precisely.     

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.     

Integrated ZVS DC–DC converter with continuous input current and high voltage gain

An integrated zero-voltage-switching (ZVS) DC–DC converter with continuous input current and high voltage gain is proposed. The proposed converter can operate with soft switching, a continuous inductor current and fixed switching frequency. The voltage stress of the power switches is relatively low compared to the output voltage. Moreover, soft-switching characteristic of the proposed converter reduces switching loss of active power switches and raise the conversion efficiency. The reverse-recovery problem of output rectifiers is also alleviated by controlling the current changing rates of diodes with the use of the leakage inductance of a coupled inductor. The operation and performance of the proposed DC–DC converter were verified on an 115?W experimental prototype operating at 100?kHz.     

A feedback loop regulated bootstrap driver circuit with improved drive capability for high voltage buck DC–DC converter

A novel bootstrap driver circuit applied to high voltage buck DC–DC converter is proposed. The gate driver voltage of the high side switch is regulated by a feedback loop to obtain accurate and stable bootstrapped voltage. The charging current of bootstrap capacitor is provided by the input power of the DC–DC converter directly instead of internal low voltage power source, so larger driver capability of the proposed circuit can be achieved. The bootstrap driver circuit starts to charge the bootstrap capacitor before the switch node SW drop to zero voltage at high-side switch off-time. Thus inadequate bootstrap voltage is avoided. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6 µm 40 V CDMOS process. The experimental results show that the bootstrap driver circuit provides 5 V stable bootstrap voltage with higher drive capability to drive high side switch. The proposed circuit is suitable for high voltage, large current buck DC–DC converter.     

A novel PWM control for a bi-directional full-bridge DC–DC converter with smooth conversion mode transitions

A novel CMOS integrated pulse-width modulation (PWM) control circuit allowing smooth transitions between conversion modes in full-bridge based bi-directional DC–DC converters operating at high switching frequencies is presented. The novel PWM control circuit is able to drive full-bridge based DC–DC converters performing step-down (i.e. buck) and step-up (i.e. boost) voltage conversion in both directions, thus allowing charging and discharging of the batteries in mobile systems. It provides smooth transitions between buck, buck-boost and boost modes. Additionally, the novel PWM control loop circuit uses a symmetrical triangular carrier, which overcomes the necessity of using an output phasing circuit previously required in PWM controllers based on sawtooth oscillators. The novel PWM control also enables to build bi-directional DC–DC converters operating at high switching frequencies (i.e. up to 10?MHz and above). Finally, the proposed PWM control circuit also allows the use of an average lossless inductor-current sensor for sensing the average load current even at very high switching frequencies. In this article, the proposed PWM control circuit is modelled and the integrated CMOS schematic is given. The corresponding theory is analysed and presented in detail. The circuit simulations realised in the Cadence Spectre software with a commercially available 0.18?µm mixed-signal CMOS technology from UMC are shown. The PWM control circuit was implemented in a monolithic integrated bi-directional CMOS DC–DC converter ASIC prototype. The fabricated prototype was tested experimentally and has shown performances in accordance with the theory.     

A 95 nA quiescent current hysteretic mode buck converter with sample and hold reference

A nano ampere (nA) hysteretic mode buck converter is presented in this paper. Nano ampere current sleep phase and fast response burst phase are implemented. The converter achieves nano-watt power consumption in sleep phase while ensures fast wake-up from sleep phase to burst phase. New developed ultra low power sample-hold voltage reference and 1 kHz oscillator draw currents of 20 and 10 nA respectively. The circuit was implemented in a 0.35 μm CMOS process. The measurement result shows that the converter’s quiescent current (Iq) in sleep phase is as low as 95 nA. Benefit from the ultra-low Iq, the circuit achieves conversion efficiency of 79.8% at 2 μA load, regulating output at 2.5 V with a 3.6 V supply. The peak efficiency is up to 94% at 50 mA load.     

Fast transient DC–DC converter with adaptive compensation zero technique

This letter is to present an adaptive compensation zero circuit to achieve good transient response in current-mode DC–DC buck converter. The proposed structure introduces an adaptive resistance dynamically adjusted according to the different output load conditions, which achieves an adequate system phase margin. A monolithic DC–DC buck converter using the proposed structure was fabricated with 0.35 μm CMOS process. Measurement results show that the transient undershoot/overshoot voltage and the recovery time do not exceed 60 mV and 20 μs for a load current variation from 0 to 1 A.     

High-accuracy current sensing circuit with current compensation technique for buck–boost converter

A novel on-chip current sensing circuit with current compensation technique suitable for buck–boost converter is presented in this article. The proposed technique can sense the full-range inductor current with high accuracy and high speed. It is mainly based on matched current mirror and does not require a large proportion of aspect ratio between the powerFET and the senseFET, thus it reduces the complexity of circuit design and the layout mismatch issue without decreasing the power efficiency. The circuit is fabricated with TSMC 0.25 µm 2P5M mixed-signal process. Simulation results show that the buck-boost converter can be operated at 200 kHz to 4 MHz switching frequency with an input voltage from 2.8 to 4.7 V. The output voltage is 3.6 V, and the maximum accuracy for both high and low side sensing current reaches 99% within the load current ranging from 200 to 600 mA.     

Adaptive duty ratio modulation technique in switching DC–DC converter operating in discontinuous conduction mode

Adaptive duty ratio (ADR) modulation technique in switching DC–DC converter operating in discontinuous conduction mode is proposed in this paper. The proposed ADR modulation technique can regulate the output voltage of the DC–DC converter by generating a series of duty ratios with very simple circuit architecture. The duty ratio is approximately proportional to the square root of the voltage difference between the regulated output voltage and the reference voltage at the beginning of the switching cycle at the light load. As a result, the proposed ADR modulation technique can achieve smaller ripple than the conventional pulse skip modulation over the whole load range. Moreover, the compromise between the light-load ripple and the output power range in the design stage in previous works is solved in the ADR modulation technique. Theoretical analysis, simulation and experimental results are presented to show the operation principle and the advantage of the proposed ADR modulation technique.     

A transient enhanced DVS DC–DC converter based on state trajectory analysis

Dynamic voltage scaling (DVS) can effectively reduce energy consumption by dynamically varying the supply voltage of the system accordingly to the clock frequency. A new DVS-enabled DC–DC converter is presented in this paper. State trajectory is employed to analyze the transient features of PWM and PFM Buck converters. A novel transient enhancement circuit is designed to improve the transient response of the DVS-enabled Buck converter. To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC–DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 μs/V and the recovery speed is 33 μs/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm × 1.33 mm in a 0.18 μm standard CMOS process.     

A wide output range voltage-mode buck converter with fast voltage–Tracking speed for RF power amplifiers

A high switching frequency voltage-mode buck converter with fast voltage-tracking speed, wide output range and PWM/PSM control strategy for radio frequency (RF) power amplifiers (PAs) has been proposed. To achieve the fast voltage-tracking speed, the maximum charging and discharging current control method has been used, and the filter inductor and capacitor values are reduced. A novel compensated error amplifier (EA) is presented to realize the wide output range. The investigated converter has been fabricated with GF 0.35 μm CMOS process and can operate at 5 MHz with the output voltage range from 0.6 V to 3.4 V. The experimental results show that the voltage-tracking speed can achieve 8.8 μs/V for up-tracking and 6 μs/V for down-tracking. Besides, the recovery time is less than 8 μs when the load change step is 400 mA.     

A current-mode buck DC–DC controller with adaptive on-time control

A current-mode buck DC–DC controller based on adaptive on-time (AOT) control is presented. The on-time is obtained by the techniques of input feedforward and output feedback,and the adaptive control is achieved by a sample-hold and time-ahead circuit. The AOT current-mode control scheme not only obtains excellent transient response speed,but also achieves the independence of loop stability on output capacitor ESR. In addition,the AOT current-mode control does not have subharmonic oscillation phenomenon seen...     

A fully integrated switched-capacitor DC–DC converter with hybrid output regulation

In this paper, we propose a fully integrated switched-capacitor (SC) DC–DC converter with hybrid output regulation that allows a predictable switching noise spectrum. The proposed hybrid output regulation method is based on the digital capacitance modulation for fine regulation and the automatic frequency scaling for coarse regulation. The automatic frequency scaler and on-chip current sensor are implemented to adjust the switching frequency at one of the frequencies generated by a binary frequency divider with change in load current. Thus, the switching noise spectrum of the proposed SC DC–DC converter can be predicted over the entire load range. In addition, the bottom-plate losses due to the parasitic capacitances of the flying capacitors and the gate-drive losses due to the gate capacitances of switches are reduced at light load condition since the switching frequency is automatically adjusted. The proposed SC DC–DC converter was implemented in a 0.13 µm CMOS process with 1.5 V devices, and its measurement results show that the peak efficiency and the efficiency at light load condition are 69.2% and higher than 45%, respectively, while maintaining a predictable switching noise spectrum.     

Robust feedforward compensation scheme with AC booster for high frequency low voltage buck DC–DC converters

Today and in the future, high frequency low voltage DC–DC converters are an effective power-management solution for fast transient response and small profile in portable electronic systems. This paper presents a robust feedforward compensation scheme with AC booster. An ac amplifier is added in parallel with the main path to compensate the high-frequency gain reduction, which improves gain-bandwidth (GBW) product and slew rate significantly. This approach takes the multistage error amplifier (EA) as an element in the compensation circuit instead of using passive elements used in traditional proportional-plus-integral-and-derivative (PID) compensation circuits. The positive phase shift of left-half-phase (LHP) zeros caused by the feedforward path and ac boosting path in the multistage EA is used to cancel the negative phase shift by the resonant poles of the power stage of buck DC–DC converter in order to compensate the DC–DC converters. A graphical loop-gain method is used to design the feedback compensation and analyze the closed-loop performances of the converter for the complexion arising from the presence of multiple poles of EA before crossover frequency in high frequency converters. The high gain, wide bandwidth, and high slew rate are achieved by the absence of traditional pole-splitting effect and the added ac booster. In addition, the design guidelines for this feedback compensation network realized by robust feedforward with AC booster compensation (RFACBC) scheme and multistage EA are established. When the proposed compensation networks were employed in 100 MHz buck DC–DC converter implemented in SMIC 0.18 μm CMOS process, the simulation results validate the feasibility and functionality of the RFACBC scheme and design guidelines. The closed-loop dc gain achieves over 60 dB with over 20 MHz GBW and 61° phase margin under wide range loads. Furthermore, the settling time is improved due to the advanced frequency compensation.     

A 200-mA, 93% peak power efficiency, single-inductor, dual-output DC–DC buck converter

A single-inductor dual-output (SIDO) DC–DC buck converter is presented. The circuit uses only one (external) inductor to provide two independent output voltages ranging from 1.2 V to the power supply (2.6–5 V) with a maximum total output current of 200 mA. The proposed converter has been fabricated in a 0.35-μm p-substrate CMOS technology. Measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved. An automatic substrate bias switch technique, that cancels the body effect of the p-channel output power transistors, improves the converter power efficiency performance.     

A multiple-output switched-capacitor DC–DC converter for individual brightness control of RGB LEDs with time-interleaved control and output current regulation

In this paper, an integrated multiple-output switched-capacitor (SC) converter with time-interleaved control and output current regulation is presented. The SC converter can reduce the number of passive components and die areas by using only one flying capacitor and by sharing active devices. The proposed converter has three outputs for individual brightness control of red–green–blue (RGB) LEDs. Each output directly regulates the current due to the V–I characteristics of LEDs, which are sensitive to PVT variations. In the proposed converter, the current-sensing technique is used to control the output current, instead of current-regulation elements (resistors or linear regulators). Additionally, in order to reduce the active area, three outputs share one current-sensing circuit. In order to improve the sensing accuracy, bias current compensation is applied to a current-sensing circuit. The proposed converter has been fabricated with a CMOS 0.13-μm 1P6M CMOS process. The input voltage range of the converter is 2.5–3.3 V, and the switching frequency is 200 kHz. The peak power efficiency reaches 71.8 % at V _IN =2.5 V, I _LED1 = 10 mA, I _LED2 = 18 mA, and I _LED3 = 20 mA. The current variations of individual outputs at different supply voltages are less than 0.89, 0.72, and 0.63 %, respectively.