A new charge-pumping technique for profiling the interface-statesand oxide-trapped charges in MOSFETs

A new charge-pumping method has been developed to characterize the hot-carrier induced local damage. By holding the rising and falling slopes of the gate pulse constant and then varying the high-level (V_GH) and base-level (V_GL) voltages, the lateral distribution of interface-states (N_it(x)) and oxide-trapped charges (Q_ox(x)) can be profiled. The experimental results show that during extracting Q_ox(x) after hot-carrier stress, a contradictory result occurs between the extraction methods by varing the high-level (V_GH) and base-level (V_GL) voltages. As a result, some modifications are made to eliminate the perturbation induced by the generated interface-states after hot-carrier stress for extracting Q_ox(x)     

A novel technique for profiling the lateral n- dopingconcentrations of submicron LDD MOS devices

This paper reports a simple I-V method for the first time to determine the lateral lightly-doped source/drain (S/D) profiles (n^- region) of LDD n-MOSFETs. One interesting result is the direct observation of the reverse-short-channel effect (RSCE). It is observed that S/D n^- doping profile is channel length dependent if reverse short-channel effect exists as a result of the interstitial imperfections caused by Oxide Enhanced Diffusion (OED) or S/D implant. Not only the lateral profiles for long-channel devices but also for short-channel devices can be determined. One other practical application of the present method for device drain engineering has been demonstrated with a LATID MOS device drain engineering work. It is convincible that the proposed method is well suited for the characterization and optimization of submicron and deep-submicron MOSFETs in the current ULSI technology     

A new method for characterizing the spatial distributions ofinterface states and oxide-trapped charges in LDD n-MOSFETs

Previous studies showed that simultaneous determination of the interface states (Nit) and oxide-trapped charges (Q_ox) in the vicinity of the drain side in MOS devices was rather difficult. A new technique which allows a consistent characterization of the spatial distributions of both hot-carrier-induced Nit and Q_ox is presented. Submicron LDD n-MOS devices were tested and charge pumping measurements were performed. The spatial distributions of both Nit and Q _ox have been justified by two-dimensional (2-D) device simulation of the I-V characteristics for devices before and after the stress. Comparison of the drain current characteristics between simulation and experiment shows very good agreement. Moreover, results show that fixed-oxide charge effect is less pronounced to the device degradation for the experimental LDD-type n-MOS devices     

Extraction of the lateral distribution of interface traps in MOSFETs by a novel combined gated-diode technique

A novel combined gated-diode technique for qualitatively extracting the lateral distribution of interface traps in N-MOSFETs is presented in this paper. The key of this technique lies in the recombination–generation current peak originating from the interface trap recombination is being modulated by the drain voltage of the combined forward gated-diode architecture. The extraction principle is introduced in detail and the extraction procedure is also erected. The experimental results qualitatively show that the induced interface traps gradually decrease from the drain and source edges to the channel region while showing the highest value near both edges in N-MOSFETs.     

Role of hot-hole injection in hot-carrier effects and the small degraded channel region in MOSFET's

Drain avalanche hot-carrier (DAHC) injection, which imposes the most severe limitations on n-channel MOS device design, is investigated from the viewpoint of surface-state generation and its localized area in the channel. It is shown, using the charge pumping technique, that the surface states are mainly created by hot-hole injection, and its small degraded area stretches toward the source region with increased stress time. A remarkable correlation between the increase of surface-state density, transconductance degradation, and substrate current is also described. In addition, to clarify the role of hot-hole injection, p-channel devices, as well as n-channel devices, are used, and hot-hole injection is shown to create more surface states than hot-electron injection.     

Influence of interface state charges on RF performance of LDMOS transistor

Si-LDMOS transistor is studied by TCAD simulation for improved RF performance. In LDMOS structure, a low-doped reduced surface field (RESURF) region is used to obtain high breakdown voltage, but it reduces the transistor RF performance due to high on-resistance. The interface charges between oxide and the RESURF region are studied and found to have a strong impact on the transistor performance both in DC and RF. The presence of excess interface state charges at the RESURF region results not only higher DC drain current but also improved RF performance in terms of power, gain and efficiency. The most important achievement is the enhancement of operating frequency and RF output power is obtained well above 1 W/mm up to 4 GHz.     

Minimized constrains for lateral profiling of hot-carrier-induced oxide charge and interface traps in MOSFETs

For better understanding the hot-carrier-induced reliability problems, a charge-pumping technique has been developed to profile the Q/sub ot/ and N/sub it/ directly from the experimental results. However, the key neutralization condition is acquired by trial and error, which takes much time and effort. Therefore, a technique of two-step neutralization is proposed to find out the appropriate neutralization condition in this work. This two-step neutralization combined with the error-reduction method is shown to carry out the profiling more quickly and precisely.     

A new technique for measuring lateral distribution of oxide chargeand interface traps near MOSFET junctions

A technique to measure the lateral distribution of both interface traps and trapped oxide charge near the source-drain junctions in MOSFETs is presented. Its basic principle is described. This technique derives from the charge-pumping method, is easy to implement, and allows ready separation of the interface-trap and oxide charge components. Examples are shown for hot-carrier stressed MOS transistors     

A novel subthreshold slope technique for the extraction of theburied-oxide interface trap density in the fully depleted SOIMOSFET

A novel experimental technique, based on the double-gate operation, is proposed for extracting the back interface trap density of the fully depleted SOI MOSFET. The method relies on simple current-voltage measurements, requires no prior knowledge of the silicon film thickness, and successfully eliminates inaccuracies arising from thickness variations of the accumulation layer, by maintaining both interfaces in depletion. The sensitivity of the technique is shown to depend on the ratio of the interface trap and oxide capacitances of the buried oxide, and is thus limited only by the buried oxide thickness. The technique has been successfully used to monitor the increase in back interface trap density following Fowler-Nordheim stress     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

A unified approach to profiling the lateral distributions of bothoxide charge and interface states in n-MOSFET's under various biasstress conditions

A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N _it) and oxide charge (Q_ox) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N_it and Q_ox in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N_it and Q_ox under various bias stress conditions, such as the hot-electron stress (I_G,max), I_B,max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N_it and Q_ox has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, E²PROM cells since the above stress conditions, such as the I_G,max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively     

A new SCCD specific measurement technique to determine the effective fast interface state density

Taking into account the thermally generated minority carriers to determine the background charge level along a SCCD, a measurement technique is described to obtain an effective fast interface state density N/SUB SSeff/. Compared to other SCCD specific methods the authors achieve better accuracy. The measurement technique is simple to apply and is useful to determine very small values of N/SUB SSeff/.     

Effects of high field generation of charge trapping in the oxideand interface traps on MOS capacitors and MOSFETs

Oxide charge trapping and interface state generation phenomena under the various high-field stress conditions have been investigated using capacitors fabricated on both p-and n-type substrates, and p- and n-channel MOSFETs. It was found that prediction based on MOSFET devices yielded shorter lifetimes than predictions based on capacitors     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

A bridge technique for memristor state programming

ABSTRACT

In order to effectively use a memristor in analog circuits, its memristance should be adjusted to a desired value between its limits. Since the maximum and minimum required memristance typically varies considerably between different types of memristors, it is almost impossible to tune the resistance of each memristor based on a reference resistor. Which is mostly done using some programmer circuits. Moreover, those programming strategies involving pulses are time-consuming and they impose high hardware headroom. In this paper, a novel CMOS circuit is presented for programming memristors. A Wheatstone bridge circuit is used to measure the current memristance, while the programming current is flowing through the device. Using such an approach reading the state and its adjustment are done simultaneously, which reduces the programming latency. In the proposed method, instead of tuning the memristance, the state of the memristor will be set to the desired value, which is proportional to a control voltage. The low programming latency, six-bit accuracy, and use of a simple circuit for programming, are the main advantages of our solution. The proposed circuit is designed and laid out in 0.35 µm CMOS technology and takes 0.0273mm². Furthermore, the proposed approach is applied to a memristor emulator to demonstrate its correct operation in real applications.     

A novel technique for the solution of second-order differenceequations

The class of second-order difference equations that arise in the diffraction of a plane wave at skew incidence on an impedance wedge is investigated. For a typical equation which was solved by the introduction of elliptic integrals, it is shown that the solution can be obtained in a very trivial manner from a convolution-type integral equation and the results are in complete agreement with those previously found     

A novel micromachining technique for the formation of extrusions

A novel micro-extrusion process (MEP) has been developed for micromachining applications. Extrusions on the micrometer scale were realized using the compressive stresses resulting from electromigration-induced mass transport in planarized conductors. Electromigration produced compressive stresses at the anodes of passivated metallic interconnects that exceeded the plastic deformation stress, and allowed extrusions to form through simple die patterns etched through the passivation at the anode ends of edge-displacement conductor segments     

Surface charge spectroscopy—A novel surface science technique for measuring surface state distributions on semiconductors

A novel technique, surface charge spectroscopy (SCS), has been developed for measuring interface state density at a dielectric-semiconductor interface in conjunction with x-ray photoelectron spectroscopy (XPS). In this technique, a thin dielectric layer with thickness up to 15 nm, is deposited on a semiconductor substrate. The surface Fermi level (E_Fs) of the semiconductor and the surface potential of the dielectric are measured using XPS, the latter of which can be varied by charging the dielectric with electrons from a low energy electron flood gun commonly equipped inside an XPS system. The interface state distribution in the band gap of the sample is then extracted from the relationship between the E_Fs and the dielectric surface potential with a simple space-charage calculation similar to the conventional capacitance-voltage technique. Experimental data on SiO₂/Si and SiN_x/InP samples are shown in the article to illustrate the applicability of SCS.     

A two-dimensional electrostatic model for degraded LDD-nMOSFETs including spatial and energy distribution of hot-carrier-induced interface traps

A two-dimensional electrostatic model for degraded short channel lightly doped drain (LDD)-nMOSFETs is presented. The model is based on a numerical solution of the Poisson equation using the five-point finite difference approximation. The model takes into account all device details including doping profiles and spatial and energy distribution of hot-carrier induced interface traps in the LDD region. Potential and charge distributions within the device in weak (subthreshold) and strong inversion regimes have been extensively studied. The validation of the model has been carried out through comparison between simulated I-V characteristics in the linear region and published experimental data. The results obtained have shown that the drain current is greatly affected by the energy distribution of interface traps, especially in the low gate voltage range (near-threshold and subthreshold).