Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead     

Reduced reverse narrow channel effect in thin SOI nMOSFETs

The effects of narrow channel width on the threshold voltage of deep submicron silicon-on-insulator (SOI) nMOSFETs with LOCOS isolation have been investigated. The reverse narrow channel effect (RNCE) in SOI devices is found to be dependent on the thickness of the active silicon film. A thinner silicon film is found to depict less threshold voltage fall-off. These results can be explained by a reduced oxide/silicon interface area in the transistor width direction, thus the boron segregation due to silicon interstitials with high recombination rate is reduced     

Novel polycrystalline silicon thin film transistors prepared by deposition from Si2H6 and subsequent annealing by NH3 plasma

This work investigated the channel layer of polycrystalline silicon (poly-Si) thin film transistors (TFTs) prepared by amorphous silicon (a-Si) films deposited using Si₂H₆ gas. The recrystallization of channel layers, source/drain, gate electrodes and post implant anneal were performed at the same time. Due to the larger grain size, the device has higher field effect mobility than SiH₄ deposited devices. These devices were also subsequently passivated by NH₃ plasma. The NH₃ plasma significantly improves the n-channel devices; however, the improvement of p-channel devices is limited. Especially, the threshold voltage of n-channel devices is significantly shifted toward the negative gate voltage than the shift magnitude of p-channel devices. To investigate the band gap width and Fermi level by determining the leakage activation energy, it is found that the channel film is changed slightly from p-type to n-type. These results may be attributed to the donor effect by NH₃ plasma passivation.     

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poisson's equation in terms of the channel length L, the silicon thickness t _Si, and the gate oxide thickness t _OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t _Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.     

Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si₃N₄ and Ta₂O₅ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si₃N₄ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta₂O₅ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta₂O₅ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta₂O₅ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation     

Numerical analysis of a PbTiO3 ferroelectric thin-filminfrared optical diode

A thin PbTiO₃-n-p⁺ silicon diode has been developed, in which the conductivity increases with the infrared light power. The infrared-sensitive part consists of PbTiO₃ ferroelectric thin film deposited by RF sputtering. The diode has smaller heat capacity compared with other conventional infrared sensors because the tunneling current is allowed through the PbTiO₃ layer so that the PbTiO₃ film thickness can be thinned. Numerical analysis of the operational mechanism, such as the effects of infrared light power on the depletion layer width, n-p⁺ junction voltage, surface depletion region voltage drop, and voltage drop across the thin PbTiO₃ film, are reported in detail. Furthermore, some experimental measurements, such as the effects of infrared light power on current-voltage (I-V) curves and the dielectric constant of PbTiO₃ film, are compared with the theoretical analysis     

Operation of SOI CMOS devices at liquid-nitrogen temperature

Liquid-nitrogen-temperature (LNT) operation of silicon-on-insulator (SOI) CMOS devices has been investigated experimentally. The maximum carrier mobilities in these devices increase by factors from 1.25 to 4.5 between room temperature and LNT. At LNT, the increase in depletion-layer width and the resulting threshold-voltage increase are limited by the silicon film thickness. For SOI devices with a body contact, the series resistance between channel and body contact increases at lower temperature, resulting in a current kink in saturation I-V characteristics     

双光栅结构薄膜太阳能电池的优化

为了提高单晶硅薄膜太阳能电池短路电流密度和转换效率, 采用在单晶硅薄膜太阳能电池正背面分别集成硅介质光栅和铝金属光栅的方法, 并利用有限时域差分法软件仿真研究了两种光栅的周期、厚度、占空比对单晶硅薄膜太阳能电池短路电流密度和光转换效率的影响。结果表明, 通过优化可得当正背面光栅都处于最优值时(介质光栅占空比F=0.8、介质光栅周期P=0.632μm、介质光栅厚度h_g=0.42μm; 金属光栅占空比F₁=0.9、金属光栅周期P=0.632μm、金属光栅厚度h_m=0.005μm), 短路电流密度可达35.15mA/cm2, 转换效率为43.35%;将最优光栅单晶硅薄膜太阳能电池与传统单晶硅薄膜太阳能电池对比, 无论是光程路径还是吸收效率, 光栅单晶硅薄膜太阳能电池都有显著的提高。这为以后制备高性能薄膜太阳能电池提供了理论指导。     

Monte Carlo simulation of electron transport properties inextremely thin SOI MOSFET's

Electron mobility in extremely thin-film silicon-on-insulator (SOI) MOSFET's has been simulated. A quantum mechanical calculation is implemented to evaluate the spatial and energy distribution of the electrons. Once the electron distribution is known, the effect of a drift electric field parallel to the Si-SiO₂ interfaces is considered. The Boltzmann transport equation is solved by the Monte Carlo method. The contribution of phonon, surface-roughness at both interfaces, and Coulomb scattering has been considered. The mobility decrease that appears experimentally in devices with a silicon film thickness under 20 nm is satisfactorily explained by an increase in phonon scattering as a consequence of the greater confinement of the electrons in the silicon film     

The behavior of narrow-width SOI MOSFETs with MESA isolation

Narrow-width effects in thin-film silicon on insulator (SOI) MOSFETs with MESA isolation technology have been studied theoretically and experimentally. As the channel width of the MOSFET is scaled down, the gate control of the channel potential is enhanced. It leads to the suppression of drain current dependence on substrate bias and punchthrough effect in narrow-width devices. The variation of threshold voltage with the channel width is also studied and is found to have a strong dependence on thickness of silicon film, interface charges in the buried oxide and channel type of SOI MOSFETs     

X波段FBAR用AlN薄膜制备研究

采用中频磁控溅射法,在硅基上制备了X波段薄膜体声波谐振器(FBAR)滤波器用AlN压电薄膜。对AlN薄膜进行了分析表征,结果表明,AlN压电薄膜具有良好的(002)面择优取向,摇摆曲线半峰宽为2.21°,膜厚均匀性优于0.5%,薄膜应力为-5.02 MPa,应力可在张应力和压应力间进行调节。将该AlN薄膜制备工艺应用于FBAR器件的制作,研制出X波段FBAR器件,谐振频率为9.09 GHz,插入损耗为-0.38 dB。     

Electron mobility behavior in extremely thin SOI MOSFET's

Extremely thin-film SOI MOSFET's with silicon film thickness down to 8 nm have been fabricated without inducing serious source/drain series resistance by employing a gate recessed structure. The influence of extremely thin silicon film on the electron mobility has been experimentally studied. The results show an abrupt mobility decrease in the device with less than 10 nm silicon film thickness. The measured mobility versus effective field below 10 nm silicon film thickness shows that a different scattering mechanism is involved in carrier conduction in 10 nm t_si region. The reasons for the mobility decrease have been examined from a device simulation and measurements     

Fully-depleted SOI devices with TaSiN gate, HfO/sub 2/ gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.     

Plasma charging damage on MOS devices with gate insulator ofhigh-dielectric constant material

Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si₃N₄ film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta₂O₅ samples. For devices with Ta₂O₅ film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application     

Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field E_I to increase the vertical breakdown voltage of a device V_B,V are presented: 1) using a thin silicon layer with a high critical electric field E_S,C ; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon epsiv_T, the formula of E_S,C on silicon layer thickness t_S is first obtained, which increases sharply with a decrease of t_S, and reaches up to 141 V/mum at t_S = 0.1 mum. Expressions for E_I and VByV are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an E_I value of 300 V/mum has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF.     

对异型硅岛实现的厚膜全耗尽SOIMOSFET的模拟研究

本文提出了用异型硅岛实现的厚膜全耗尽(FD)SOI MOSFET的新结构,并分析了其性能与结构参数的关系.通过在厚膜SOI MOSFET靠近背栅的界面形成一个相反掺杂的硅岛,从而使得厚膜SOI MOSFET变成全耗尽器件.二维模拟显示,通过对异型硅岛的宽度、厚度、掺杂浓度以及在沟道中位置的分析与设计,厚膜SOI MOSFET不仅实现了全耗尽,从而克服了其固有的Kink效应,而且驱动电流也大大增加,器件速度明显提高,同时短沟性能也得到改善.模拟结果证明:优化的异型硅岛应该位于硅膜的底部中央处,整个宽度约为沟道长度的五分之三,厚度大约等于硅膜厚度的一半,掺杂浓度只要高出硅膜的掺杂浓度即可.重要的是,异型硅岛的设计允许其厚度、宽度、掺杂浓度以及位置的较大波动.可以看出,异型硅岛实现的厚膜全耗尽 SOI MOSFET 为厚膜SOI器件提供了一个更广阔的设计空间.     

Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI

In this letter, based on both experimental investigations and simulation confirmation, it was found that a strained contact etch stop layer over the thin silicon layer of a partially depleted silicon-on-insulator (PD-SOI) will induce high stress on the buried-oxide/silicon interface. Additionally, the interface stress increases with decrease of silicon thickness T_SI, thus enhancing the current of the MOSFET, e.g., as T_SI shrinks from 90 to 50 nm, current enhancement for PD-SOI n-channel MOS increased from 7% to 12% due to the increase of interface stress. The results are expected to be more significant for devices with thinner T_SI such as fully depleted silicon-on-insulator and multigate devices     

Stable gallium arsenide MIS capacitors and MIS field effecttransistors by (NH4)2Sx treatment andhydrogenation using plasma deposited silicon nitride gate insulator

The beneficial effects of sulfur passivation of gallium arsenide (GaAs) surface by (NH₄)₂S_x chemical treatment and by hydrogenation of the insulator-GaAs interface using the plasma-enhanced chemical vapor-deposited (PECVD) silicon nitride gate dielectric film as the source of hydrogen are illustrated by fabricating Al/PECVD silicon nitride/n-GaAs MIS capacitors and metal insulator semiconductor field effect transistors (MISFET). Post metallization annealing (PMA) at temperatures in the range 450-550°C is shown to be the key process for achieving midgap interface state density below 10 ¹¹/cm²/eV and maximum incremental transconductance, which is about 75% of the theoretical maximum limit. MIS capacitors are fabricated on (NH₄)₂S_x treated GaAs substrate using gate dielectrics such as PECVD SiO ₂ and silicon oxynitride to demonstrate that the PMA is less effective with these dielectrics because of their lower hydrogen content. The small signal AC transconductance, g_ms measurements on MISFETs fabricated using silicon nitride, have shown that the low-frequency degradation of g_ms is almost absent in the devices fabricated on (NH₄)₂S_x-treated GaAs substrates and subjected to PMA. The drain current stability in these devices is demonstrated to be excellent, with an initial drift of only 2% of the starting value. The dual role of silicon nitride layer, namely, protection against loss of sulfur and an excellent source of hydrogen for additional surface passivation along with sulfur is demonstrated by comparing the transconductance of MISFETs fabricated on GaAs substrates annealed without the nitride cap after the (NH₄)₂S _x treatment     

Analysis of drying shrinkage and flow due to surface tension ofspin-coated films on topographic substrates

In semiconductor manufacturing processes, it is important that the SiO₂ isolation films around aluminum connection lines have flat surfaces in order to produce the multilayered connection lines used in high-density devices. In this paper, we analyzed transient changes, in the thickness distributions of a liquid-SOG (Spin-on-Glass) film on a two-dimensionally (2-D) grooved substrate during the evaporative shrinking process. The flow due to surface tension of the shrinking liquid film was calculated. Since the film is thin, a boundary layer approximation could be applied, and fourth-order differential equations of film thickness were solved using an iteration method. The viscosity and the shrinkage rate were assumed to be functions of the concentration of the solvent in the film. When the parameter of ratio [(surface tension)/{(viscosity)×(shrinking speed)}] is large and the width of the grooves is small, final surface undulations of the film are shallow. The effect of the centrifugal force was also analyzed     

硅基高精度镍铬薄膜电阻的制备和性能表征

集成无源元件（IPD）技术可以将分立的无源元件集成在衬底内部,提高系统的集成度。为了获得高精度的薄膜电阻,采用多层薄膜电路工艺在硅晶圆上制备了不同线宽的镍铬薄膜电阻,利用显微镜和半导体参数测试仪对薄膜电阻的图形线宽及电学特性进行了表征及测试。结果表明,制备出的镍铬薄膜电阻线宽精度在±5%以内,电阻精度在±0.5%以内,具有稳定的电学特性。基于镍铬的高精度硅基无源集成电阻器在系统集成中有广泛的应用价值。