Study on the performance of sub 100 nm LACLATI MOSFETs for digital application

With the help of extensive simulations, we systematically investigated the effects of varying tilt angle of halo implant in sub 100 nm lateral asymmetric channel (LAC) MOSFETs on the reverse short channel effects, the on current and the hot carrier immunity. The devices with large angle tilt implants also show the substantial reduction in the subthreshold swing, improvement in I_ON/I_OFF ratio and significantly the lower junction capacitance as compared to the devices with low angle tilt implant. It is also observed that the subthreshold characteristics do not change as the channel length decreases for such devices. These devices, known as lateral asymmetric channel with large angle tilt implant (LACLATI), will therefore have much improved performance in comparison to a low angle tilt implant LAC devices for digital applications.     

Organic memristive devices based on silver nanoparticles and DNA

A novel organic memory device ‘Al/silver nanoparticles-deoxyribonucleic acid-cetyltrimethylammonium Bromide/ITO’ (Al/Ag NPs–DNA–CTMA/ITO) was fabricated. The measured I–V curve of the device exhibits unipolar switching. The conductivity and the memristive characteristics are significantly improved by the introduction of Ag nanoparticles, but with a poor stability. Better stability is achieved by annealing the device, which also changes the switching characteristic from unipolar to bipolar. As the annealing temperature is raised, the switching voltage first decreases and then increases, while the current I_RESET first increases and then decreases. The range of the optimal annealing temperature is from 383 K to 403 K and the maximum ON/OFF current ratio (I_ON/I_OFF) can reach 10⁴. The switching voltage, the current, and I_ON/I_OFF all increase with the applied voltage amplitude, and V_SET and I_ON/I_OFF obey a quadratic and Boltzmann relationship, respectively.     

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

Drive current boosting of n-type tunnel FET with strained SiGe layer at source

Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60 mV/decade subthreshold swing and very small OFF current (I_OFF), its practical application is questionable due to low ON current (I_ON) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60 mV/decade subthreshold swing along with a significant improvement in I_ON. The enhancement in I_ON is achieved by introducing a thin strained SiGe layer on top of the silicon source. Through 2D simulations it is observed that the device is nearly free from short channel effect (SCE) and its immunity towards drain induced barrier lowering (DIBL) increases with increasing germanium mole fraction. It is also found that the body bias does not change the drive current but after body current gets affected. An I_ON of and a minimum average subthreshold swing of 13 mV/decade is achieved for 100 nm channel length device with 1.2 V supply voltage and 0.7 Ge mole fraction, while maintaining the I_OFF in fA range.     

Performance enhancement of core-shell JLFET by gate/dielectric engineering

ABSTRACT

In this paper, enhancement of volume depletion is studied on P-type double gate junctionless Field Effect Transistor (P-DGJLFET) by Gate work function and Gate dielectric engineering. The formation of parasitic BJT action in junctionless device along with DIBL effect is curtailed by integrating Rectangular Core-Shell (RCS) architecture with varying core doping along with different gate oxides and electrodes, respectively. After validating our simulations with the experimental results on Junctionless P-type FET, we demonstrated that RCS based P-DGJLFET with high K dielectric and aluminium as gate electrode exhibits superior ON/OFF ratio, Lower DIBL, better ON current, good OFF current and desired threshold voltage at channel length 5 nm. An exceptional ON/OFF current ratio (I_ON/I_OFF) of 10¹⁰ is achieved when core is made thicker than shell. The DIBL is reduced by 62.5% when thin core along with SiO₂ is replaced by thick core and HfO₂. Also, the stringent requirement of lower work function in Junctionless P-type is relaxed using RCS architecture. The performance of RCS with polysilicon as gate electrode is better than conventional DGJLFET with aluminium as gate electrode. A comprehensive comparison on performances between different technology boosters applied on double gate JLT in the literature and proposed device is also presented.     

Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics

Schottky barrier SOI-MOSFETs incorporating a La₂O₃/ZrO₂ high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10¹¹ eV⁻¹ cm⁻², a low subthreshold slope of 70-80 mV/decade, and an I_ON/I_OFF current ratio greater than 2 × 10⁶ are obtained.     

Evaluation of process parameter space of bulk FinFETs using 3D TCAD

Using full 3D TCAD, an evaluation of process parameter space of bulk FinFET is presented from the point of view of DRAM, SRAM and I/O applications. Process and device simulations are performed with varying uniform fin doping, anti-punch implant dose and energy, fin width, fin height and gate oxide thickness. Bulk FinFET architecture with anti-punch implant is introduced beneath the channel region to reduce the punch-through and junction leakage. For 30 nm bulk FinFET, anti-punch implant with low energy of 15 to 25 keV and dose of 5.0 × 10¹³ to 1.0 × 10¹⁴ cm⁻² is beneficial to effectively suppress the punch-through leakage with reduced GIDL and short channel effects. Our simulations show that bulk FinFETs are approximately independent of back bias effect. With identical fin geometry, bulk FinFETs with anti-punch implant show same I_ON-I_OFF behavior and approximately equal short channel effects like SOI FinFETs.     

NBTI and hot carrier effect of Schottky-barrier p-MOSFETs

The experimental investigation of NBTI and hot carrier induced device degradation in Pt-silicided Schottky-barrier p-MOSFETs has been performed. The investigations on the threshold voltage shifts, the degradation of inverse subthreshold slope, and the decrease of I_ON/I_OFF ratio have been carried out using the modulation of Schottky-barrier height and width. After NBTI and hot carrier stress, the decrease of I_ON could be explained by the lower hole tunneling current through the more increased Schottky-barrier height and the increased I_OFF could be explained by the increase of the amount of electron thermal emission and tunneling through thinner Schottky-barrier into the near drain. After hot carrier stress, it is observed that the threshold voltage shifts to more negative values for all stress gate voltages and the drain current is decreased. The device degradation is more significant as the stress gate voltage decreases.     

The Design of an Intelligent High-Speed Loom Industry Interconnection Remote Monitoring System

This work proposed the design of low power Si_0.7Ge_0.3 pocket Junction-less TFET (JLTFET) on bulk silicon using below 5 nm technology. The inclusion of junction-less regions improves ON-state current with lesser effect on OFF-state current. The p-type pocket regions added to improve device performance in subthreshold region showing reduction in OFF-state leakage current leading to good value of ON/OFF current ratio as compared to other similar TFET structures. A high-value I_ON/I_OFF ratio and good subthreshold behavior are observed for pocket JLTFET with 2 nm gate length and body thickness 0.5 nm. The proposed JLTFET is further optimized for different gate contact and oxide materials. The temperature analysis plays major role in deciding a reliable ON-state and OFF-state performance of transistors. So, the proposed pocket JLTFETis investigated for harsh temperature conditions to characterize the performance for DC and AC parameters. The sensitivity of proposed JLTFET is analyzed under different temperature conditions in range of (200–400) K to observe subthreshold performance such as transfer characteristics, Output characteristics and I_ON/I_OFF ratio. The proposed designs for JLTFETs have been simulated using TCAD 2D/3D device simulator.

     

Reconnoiter the leavening of skin-deep insulated extension on analog performance of RingFET (SDIE-RingFET)

In the present work, a novel device architecture Skin Deep Insulated Extension-RingFET (i.e. SDIE-RingFET) has been reported that incorporates the better known dielectric pocket in RingFET architecture. Various analog performance matrices like I_ON/I_OFF, V_th roll off, Sub-threshold slope (SS), Device efficiency (g_m/I_ds), conduction band energy (CBE) and electron temperature (T_E) have been studied to investigate the impact of Skin Deep Insulated Extension (SDIE) on RingFET architecture. Insulated extension enhances the immunity of the device against Short Channel Effects by reducing I_OFF and providing a higher I_ON/I_OFF ratio apart from improved threshold voltage roll-off. In addition, SDIE also prevents dopant diffusion from source/drain to bulk, thereby alleviating the bulk punch-through effect and hence DIBL.     

Substrate bias and operating temperature effects on the performance of Schottky-barrier SOI nMOSFETs

The substrate bias and operating temperature effects on the performance of erbium-silicided Schottky-barrier SOI nMOSFETs have been studied. The temperature dependence of the threshold voltage, the current ratio of I_ON/I_MIN, and the subthreshold swing has been investigated. From temperature dependence of the drain current, it is confirmed that the carrier transport mechanism changes from thermionic emission and tunneling at low gate voltage to drift-diffusion at the high gate voltage. By applying substrate bias voltage, the I_ON/I_MIN ratio and subthreshold swing can be improved. By investigating the substrate bias dependence of I_ON/I_MIN ratio, subthreshold swing, and DIBL, the optimum substrate bias voltage is suggested.     

Effects of zirconium doping on the characteristics of tin oxide thin film transistors

Thin-film transistors (TFTs) with zirconium-doped tin oxide (ZSO) channels were fabricated by co-sputtering Sn and Zr metal targets. The effect of Zr on the performance of SnO_x-based TFTs was studied. TFTs with an intrinsic SnO_x channel did not show promising performance. However, ZSO TFTs exhibited improved electrical properties, with increased I_ON/I_OFF and decreased subthreshold swing. The influence of zirconium doping on bias stability in tin oxide TFTs was also investigated. ZSO TFTs exhibited turn-on voltage (V_ON) shifts of +9 V for positive stress bias, compared with +18 V for intrinsic SnO_x TFTs. The improvements in device performance and stability were attributed to reduced carrier concentration induced by carrier trapping at Zr impurity sites.     

Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires

In this paper, we report the fabrication and the electrical characterization of Vertical Gate All Around Field-Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the Vapour-Liquid-Solid (VLS) mechanism as conduction channel. The SiNWs GAA-FET devices exhibited n-channel type semiconductor behaviour whereas the as-grown SiNW FET present p-type behaviour. This effect may be due to positive fixed charge located in the oxide shell or at the Si/SiO₂ interface. Moreover we show that the threshold voltage at room temperature is around −0.95 V, a high I_ON/I_OFF ratio up to 10⁶ with a low I_OFF current about 1 pA, a maximum transconductance (g_m,max ∼ 0.9 μS at V_GS = −0.65 V and V_DS = 1 V) and a minimum inverse subthreshold slope around 145 mV/decade. In light of these characteristics, these devices can be suitable for high performance, low power consumption components and especially for high density integration in integrated circuits (ICs) interconnections regarding to their 3D architecture.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

New opportunities for SiGe and Ge channel p-FETs

A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled high-κ gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding drive current enhancement reported by Irisawa et al. [1] for narrow-width devices was investigated on these structures. Although the strained FDSGOI device structure exhibited reduced off-state leakage compared to thicker body devices, and long-channel drive current enhancement under uniaxial strain, the loss of drive current enhancement at short channel length led to uncompetitive I_ON-I_OFF characteristics. The SiGe on SOI structure showed the highest long-channel drive current enhancement (nearly 3×) in the narrowest devices, and also showed a significant reduction in off-state current. This trend was maintained down to the shortest channel lengths studied here and resulted in I_ON-I_OFF characteristics that were competitive with contemporary uniaxial strained Si channel devices.     

Investigation of scalability of In0.7Ga0.3As quantum well field effect transistor (QWFET) architecture for logic applications

In this paper, the scalability of In_0.7Ga_0.3As QWFET is investigated using two-dimensional numerical drift-diffusion simulation. Numerical drift-diffusion simulations were calibrated using experimental results on short-channel In_0.7Ga_0.3As QWFETs [7] to include the effects of velocity overshoot. Logic figures of merit (sub-threshold slope, saturated threshold voltage, drain induced barrier lowering, I_ON/I_OFF ratio over a specified gate swing, effective injection velocity and intrinsic switching delay) extracted from the numerical simulations are in excellent agreement with the experimental data. Three alternate QWFET device architectures are proposed and thoroughly investigated for 15 nm node and beyond logic applications. Amongst them, double-gate In_0.7Ga_0.3As QWFET shows the best scalability in terms of logic figures of merit, thus making it an ideal candidate for the design and demonstration of the ultimate scaled transistor.     

Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale planar MOSFET and bulk FinFET devices

Impact of the intrinsic fluctuations on device characteristics, such as the threshold voltage (V_th) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced V_th fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO₂ for the 1.2 and 0.8 nm EOTs, Al₂O₃ for the 0.4 nm EOT and HfO₂ for the 0.2 nm EOT) are then for the first time compared with the results of 16 nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property. Result of this study confirms the suppression of V_th fluctuations with the gate oxide thickness scaling (using high-κ dielectric). It is found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device’s scaling and have potential in the nanoelectronics application.     

Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON

For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (T_inv = 1.2 nm). A detailed DC analysis of I_on vs. I_off shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (V_T) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates.     

Advantage of further scaling in gate dielectrics below 0.5 nm of equivalent oxide thickness with La2O3 gate dielectrics

N-type metal-oxide-semiconductor field-effect transistor (MOSFET) with an equivalent oxide thickness (EOT) of 0.37 nm has been demonstrated with La₂O₃ as a gate dielectric for the first time. Despite the existence of parasitic capacitances at gate electrode and inversion layer in the channel, a sufficient drain current increment in both linear and saturation regions have been observed, while scaling the gate oxide from 0.48 to 0.37 nm in EOT. Therefore, continuous scaling of EOT below 0.5 nm is still effective for further improvement in device performance.     

Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications

Due to their excellent scalability and better immunity to short channel effects, double-gate (DG) MOSFETs are being earnestly assessed for CMOS applications beyond the 70 nm node of the SIA roadmap. However for channel lengths below 100 nm, DG MOSFETs still show considerable threshold voltage roll off and to overcome this effect, different gate or channel engineering techniques can be widely used. In this paper, the analog and RF performance of a single halo double gate MOSFET implemented with dual-material gate (DMG) technology is investigated with 2D device simulator. This novel structure shows better immunity to short-channel effects like DIBL and improved analog and RF performance. Moreover they exhibit better suppression of hot carrier effect and higher carrier transport efficiency than a single halo double gate MOSFET. The suitability of nanoscale single halo double gate MOSFETs with dual-material gate for circuit applications is examined by comparing the performance of a two stage cascode amplifier and a greater improvement is observed for single halo dual-material DG MOSFET compared to that of the single halo counterpart.