Design and analysis of noise margin,write ability and read stability of organic and hybrid 6-T SRAM cell

This paper analyzes SRAM cell designs based on organic and inorganic thin film transistors (TFTs). The performance in terms of static noise margin (SNM), read stability and write ability for all-p organic (Pentacene–Pentacene), organic complementary (Pentacene–C₆₀) and hybrid complementary (Pentacene–ZnO) configurations of SRAM cell is evaluated using benchmarked industry standard Atlas 2-D numerical device simulator. Moreover, the cell behaviour is analyzed at different cell and pull-up ratios. The electrical characteristics and performance parameters of individual TFT used in SRAM cell is verified with reported experimental results. Furthermore, the analytical result for SNM of all-p organic SRAM cell is validated with respect to the simulated result. Besides this, the cell and pull-up ratios of the hybrid and organic SRAM cells are optimized for achieving best performance of read and write operations and thereafter, the results are verified analytically also. The SNM of hybrid cell is almost two times higher than the all-p SRAM, whereas this improvement is just 18% in comparison to the organic memory cell. On the other hand, the organic complementary SRAM cell shows an improvement of 26% and 22% for the read stability in comparison to the all-p organic and hybrid SRAM cells, respectively. Contrastingly, this organic cell demonstrates a reduction of 16% in the SNM and an increment of 76% in write access time in comparison to the hybrid cell. To achieve an overall improved performance, the organic complementary SRAM cell is designed such that the access transistors are pentacene based p-type instead of often used n-type transistor. Favorably, this organic SRAM design shows reasonably lower write access time in comparison to the cell with n-type access OTFTs. Moreover, this cell shows adequate SNM and read stability that too at substantially lower width of p-type access OTFTs.     

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations.     

超深亚微米无负载四管与六管SRAM SNM的对比研究

采用基于物理的α指数MOSFET模型与低功耗传输域MOSFET模型，推导了新的超深亚微米无负载四管与六管SRAM存储单元静态噪声容限的解析模型．对比分析了由沟道掺杂原子本征涨落引起的相邻MOSFET的阈值电压失配对无负载四管和六管SRAM单元静态噪声容限的影响。     

A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

Technology enhancement has increased sensitivity of process variations of scaled SRAM on the verge of instability. This demands a process variation (PV) aware stability model for the modern SRAM. This paper first analyzes PV severity on readability, writability and static leakage current and provides a statistical model. The paper further improves the proposed model by using curve fitting method for stability modeling and modified Least Mean Square with first order differentiation to extract best fitting parameters. The resulting model exhibits characteristics of standard current voltage equation based model. A evolutionary optimization technique is proposed to achieve optimal cell dimension for process tolerant SRAM. The resulting SRAM is tested for worst case stability analysis using Gaussian distribution based statistical approach. Simulation results show that the resulting optimized SRAM improves read, standby and word line write margins by 4%, 4% and 23%, respectively.     

6-T CMOS SRAM单元稳定性分析及设计优化

介绍了一种由两个交叉耦合反向器构成的6-晶体管(6-T)存储单元的噪声容限分析方法.对6-T CMOS SRAM单元的稳定性作了分析及仿真.借助SPICE和MATLAB工具,对存储单元在数据保持和数据读取时的稳定性、数据写入过程中的可靠性及其之间的关系进行了深入研究.对可能影响噪声容限的因素,如单元比、上拉比、MOS管的阈值电压、位线预充电压、电源电压以及温度进行了仿真讨论,并从中得到合适的电路设计参数.流片结果表明,理论分析与实测数据相符.分析数据对基于CSMC O.5μm CMOS工艺的SRAM电路设计优化具有指导作用.     

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (V_WL) is internally reduced with respect to the cell and bit-line voltages that are maintained at nominal V_DD. A specific V_WL can be determined for each memory region, thus allowing for an adaptive approach. The benefits and drawbacks of the technique on the overall memory performance are thoroughly investigated through both simulations and experimental data. Simulations results show that this technique expands the read margin without an appreciable increase of memory area. Specifically, an improvement of 52.6% in static noise margin and a 24.5% in critical charge (parameter used to account for the dynamic stability) has been achieved with a V_WL reduction of 20%. The impact of variability on SNM is reduced, while both read and write delay increase by a specific amount that should be considered as a tradeoff when setting the word-line voltage value. A 16Kbit SRAM test chip including the proposed technique has been fabricated in a 65 nm CMOS technology. Silicon measurements confirm that the proposed technique improves cell stability during READ, which allows operating at relatively low values of V_WL with a small impact on read time.     

Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM

In recent years, much emphasis is given for low power memory design by reducing leakage power. Carbon nanotube field effect transistor (CNTFET) based static random access memory (SRAM) provides better stability along with low static power consumption due to variable bandgap and threshold voltage as function of diameter. Electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET) accounts for much low leakage current and hence can be used for low power SRAM design. This paper proposes a novel design of ED-SBCNTFET based low power SRAM which consists of additional polarity gates. 6-T SRAM cell is designed and simulated in HSPICE for both conventional CNTFET and ED-SBCNTFET. SRAM performance is analyzed on the basis of various figures of merit i.e. stability and power dissipation. ED-SBCNTFET SRAM shows advantage of low power over conventional CNTFET SRAM without loss of stability. Furthermore, SRAM is designed for smaller diameter which gives ultra low power cell with minute change in stability. Lastly dual chirality scheme is implemented and analyzed for ED-SBCNTFET 6-T SRAM cell.     

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays

Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra low-power-supply voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active-mode energy consumption. Temperature-adaptive dynamic supply voltage tuning (TA-DVS) technique is proposed in this paper to reduce the high-temperature energy consumption of ultra low-voltage subthreshold SRAM arrays. Results indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures. The impact of the temperature-adaptive dynamic supply voltage scaling technique on the data stability of the subthreshold SRAM bit-cells is presented. The effectiveness of the TA-DVS technique under process parameter and supply voltage variations is evaluated. An alternative technique based on temperature-adaptive reverse body bias (TA-RBB) to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption characteristics of the two temperature-adaptive voltage tuning techniques are compared.     

Logical effort based dynamic power estimation and optimization of static CMOS circuits

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates, sizes and processes, the developed model shows a good agreement with Hspice simulations using BSIM3v3 and BSIM4 models for UMC 0.13 μm and Predictive high-k 45 nm processes, respectively. The average error introduced by the model for the considered scenarios is about 3.1%. Depending on the normalized switching power model, two power optimization techniques have been proposed in this paper. The first deals with transistor sizing problem and presents a scheme to size transistors according to a specific design goal. The second technique relies on the joint transistor sizing and supply voltage scaling for reducing the switching power dissipation under specific delay requirements. This technique exhibits superiority over the first for the considered technology processes: UMC 0.13 μm and the Predictive high-k 45 nm.