Modeling single event crosstalk speedup in nanometer technologies

With advances in CMOS technology, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. In addition, coupling effects among interconnects can cause SE transients to spread electronically unrelated circuit paths which may increase the SE Susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work reports on the signal speedup effects caused by SE crosstalk and then proposes a best-case delay estimation methodology for use in design automation tools for the first time to our knowledge. The SE coupling speedup expressions derived show very good results in comparison to HSPICE results. Results show an average error of about 8.42% for best-case delay while allowing for very fast analysis in comparison to HSPICE.     

Single event crosstalk prediction in nanometer technologies

As CMOS technology continues to scale down, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. On the other hand, coupling effects among interconnects can cause single event transients to contaminate electronically unrelated circuit paths which may increase the SE susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event hardening, modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work, for the first time, proposes an SE crosstalk noise estimation method for use in design automation tools. The proposed method uses an accurate 4-π model for interconnect and correctly models the effect of non-switching aggressors as well as aggressor tree branches noting the resistive shielding effect. The SE crosstalk noise expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is about 5.2% while allowing for very fast analysis in comparison to HSPICE.     

Coupling induced soft error mechanisms in nanoscale CMOS technologies

Due to scaling induced effects, CMOS circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. Researchers mostly considered SE transients as the main cause for combinational logic (CL) related radiation-induced soft errors. However, for high-reliability applications such as avionics, military and medical applications, additional sources such as SE induced soft delays, clock jitters, false clock pulses and crosstalk effects need to be included in soft-error reliability analysis. As technologies advance, coupling effects among interconnects increasingly cause SE transients to contaminate electronically unrelated circuit paths, which can in turn increase the “SE susceptibility” of CMOS circuits. This work focuses on such coupling induced soft error mechanisms in CL, namely the SE crosstalk noise and delay effects. An attempt has been made to compare SE crosstalk noise and SE transient effects, and crosstalk contribution to soft error rate has been examined. In addition, the SE induced coupling delay effect has been studied and compared to radiation induced soft delay effect for various technologies. Results show that, in newer technologies, the SE coupling delay becomes quite comparable to soft delay effect, although caused indirectly by cross-coupling effects. In comparisons, the distributed nature of interconnects has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies.     

Mitigation for single event coupling delay

With advances in CMOS technology, circuits are increasingly more sensitive to transient pulses caused by single event particles. It has been predicted that the majority of the observed radiation induced soft failures in technologies below 65 nm will be because of transients that will occur in combinational logic (CL) circuits. Researchers mostly consider single event transients as the main source for CL related radiation-induced soft errors. However, for high reliability applications such as avionics additional sources need to be included in reliability analysis. In this work, we report a new error mechanism named ‘single event crosstalk delay’, investigate the vulnerability of recent technologies to these delay effects and then propose hardening techniques for single event crosstalk delay. Results are demonstrated using HSpice simulations with interconnect and device parameters derived in 130, 90 and 65 nm technology.     

Experimental results and modeling techniques for substrate noise inmixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

用SOI技术提高CMOS SRAM的抗单粒子翻转能力

提高静态随机存储器（SRAM）的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅（SOI）基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61．8MeV／（mg／cm^2）,优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。     

The design of radiation-hardened ICs for space: a compendium ofapproaches

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ICs     

INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.     

Reliability for nanomagnetic logic (NML) readout circuit under single event effect

In the application for the space radiation environment, NML circuits face a reliability challenge mainly from their CMOS peripheral circuits, suffering from single event effects (SEE). An on-chip readout interface circuit (RIC) for NML circuit is designed based on dual-barrier magnetic tunnel junction (DB-MTJ). The sensitive nodes to SEE in RIC are analyzed. The SEU required critical charge in RIC is described. The impacts of energetic particle hitting time and technology node on the critical charge are studied. As the technology node scales down, the critical charge will significantly decrease. Two efficient hardening technologies for RIC are presented: local transistors׳ size and symmetrical load capacitances. By increasing local transistors׳ size or decreasing the load capacitance, the critical charge will be improved, which enhances the immunity to SEE.     

脉冲激光试验评估模拟电路单粒子效应

利用脉冲激光对典型模拟电路的单粒子效应进行了试验评估及加固技术试验验证,研究2种不同工艺的运算放大器的单粒子瞬态脉冲(SET)效应,在特定工作条件下两者SET脉冲特征规律及响应阈值分别为79.4 pJ和115.4 pJ,分析了SET脉冲产生和传播特征及对后续数字电路和电源模块系统电路的影响。针对SET效应对系统电路的危害性,设置了合理的滤波电路来完成系统电路级加固,并通过了相关故障注入试验验证,取得了较好的加固效果。     

Ultra-low power FinFET-based domino circuits

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.     

Analysis of crosstalk interference in CMOS integrated circuits

The authors show how crosstalk coupling between transmission lines inside CMOS integrated circuits can provoke faulty behavior by affecting the propagation delay of the logic and analog cells. A simplified model for the evaluation of parasitic capacitive coupling effects is proposed, and the influence of crosstalk on the behavior of basic functions such as logic gates, latches, RAM memory, and analog-to-digital converters is evaluated     

基于时序优先的电路容错混合加固方案

为了有效降低容忍软错误设计的硬件和时序开销,该文提出一种时序优先的电路容错混合加固方案。该方案使用两阶段加固策略,综合运用触发器替换和复制门法。第1阶段,基于时序优先的原则,在电路时序松弛的路径上使用高可靠性时空冗余触发器来加固电路;第2阶段,在时序紧张的路径使用复制门法进行加固。和传统方案相比,该方案既有效屏蔽单粒子瞬态(SET)和单粒子翻转(SEU),又减少了面积开销。ISCAS89电路在45 nm工艺下的实验表明,平均面积开销为36.84%,电路平均软错误率降低99%以上。     

The twin-transistor noise-tolerant dynamic circuit technique

This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35-μm CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1.8×(for an AND gate) and 2.5×(for an adder carry chain) over domino at the same speed. A multiply-accumulate circuit has been designed and fabricated using a 0.35-μm process to verify this technique. Experimental results indicate that the proposed technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4x) with only a modest increase in power dissipation (15%) and no loss in throughput     

Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design

Exponential increase in leakage power has emerged as a major barrier to technology scaling. Existing circuit techniques for leakage reduction either suffer from reduced effectiveness at nanometer technologies or affect performance and gate-oxide reliability. In this paper, we propose application of a specific carbon nanotube (CNT)-based nano-electromechanical switch as a leakage-control structure in logic and memory circuits. In case of memory circuits, we demonstrate that the proposed hybridization can be employed to reduce both cell leakage and bitline leakage, thereby improving the read noise margin as well. Due to the unique electromechanical properties of CNTs, these switches have high current-carrying capacity, extremely low leakage current, and low operating voltages. Moreover, they can act as nonvolatile memory elements, which can be exploited for data retention of important registers and latches during power down. Simulation results for a set of benchmark circuits show that we can obtain several orders of magnitude improvement in leakage saving in logic circuits at iso-performance compared to existing multi-threshold CMOS technique. In memory circuits, simulations show reduction in standby leakage and reduction in bitline leakage compared with the best existing techniques.     

Low-power CMOS digital design

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption     

微小卫星单粒子闩锁防护技术研究

对于在轨微小卫星而言,单粒子闩锁(Single Event Latchup,SEL)是最具破坏性的单粒子效应之一,其后果轻则损坏器件,重则使在轨卫星失效。首先介绍了SEL发生机理,分析并总结现有抗SEL的关键技术。其次提出了空间单粒子闩锁防护措施并设计了一种可恢复式抗SEL电源接口电路,实现对卫星星上设备的防闩锁及过流保护。最后利用脉冲激光模拟单粒子效应技术对具有飞行经验的芯片进行实验测试。实验结果表明,该电路能够准确地检测SEL的发生,有效解除SEL效应,保证系统运行稳定可靠。     

Hybrid time and hardware redundancy to mitigate SEU effects on SRAM-FPGAs: Case study over the MicroLAN protocol

SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets caused by high-energy space radiation. Single Event Upset (In order to successfully deploy the SRAM-FPGA based designs in aerospace applications, designers need to adopt suitable hardening techniques. In this paper, we describe novel hybrid time and hardware redundancy (HT&HR) structures to mitigate SEU effects on FPGA, especially digital circuits that are designed with bidirectional ports. The proposed structures that combine time and hardware redundancy decrease the SEU propagation mechanisms among the redundant hard units. Analysis results and fault injection experiments on some standard ISCAS benchmarks and MicroLAN protocol, as a case study over the bidirectional ports, show that the capability of tolerating SEU effects in HT&HR technique increases up to 70 times with respect to solely hardware redundant versions. On average, the proposed method provides 39.2 times improvement against single upset faults and 14.9 times for double upset faults; however it imposes about 14.7% area overhead. Also, for the considered benchmarks, HT&HR circuits become 8.8% faster on the average than their TMR versions.     

A minimum total power methodology for projecting limits on CMOS GSI

A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact “transregional” MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling