A review of board level solder joints for mobile applications

The reliability of electronics under drop-shock conditions has attracted significant interest in recent years due to the widespread use of mobile electronic products. This review focuses on the drop-impact reliability of lead-free solder joints that interconnect the integrated circuit (IC) component to the printed circuit board (PCB). Major topics covered are the physics of failure in drop-impact; the use of board level and component level test methods to evaluate drop performance; micro-damage mechanisms; failure models for life prediction under drop-impact; modelling and simulation techniques; and dynamic stress–strain properties of solder joint materials. Differential bending between the PCB and the IC component is the dominant failure driver for solder joints in portable electronics subjected to drop-impact. Board level drop-shock tests correlate well with board level high speed cyclic bending tests but not with component level ball impact shear tests. Fatigue is the micro-damage mechanism responsible for the failure of solder joints in the drop-shock of PCB assemblies and the fatigue strength of solder joints depends strongly on the strain rate, test temperature, and the sequence of loading. Finally, tin-rich lead-free solders exhibit significantly higher strain rate sensitivity than eutectic SnPb solder.     

Tri-Layer Structures Subjected to Combined Temperature and Mechanical Loadings

Thermal stress has been a concern in electronic packaging for decades. More recently, mechanical bending of printed circuit board (PCB) assembly has attracted increased interest due to the drop impact failure of interconnects in mobile products. Analytical solutions are available in the literatures for a PCB assembly modeled as a tri-layer structure, consisting of IC components, PCBs, and an interconnect layer, subjected to either thermal stress or mechanical bending, but there are no known reports for combined loadings. This paper presents a comprehensive treatment for a PCB assembly subjected to combined temperature and mechanical loadings, taking into account the axial, shear, and flexural deformation of the interconnects. Solutions are provided for two types of interconnect layer: one in which the interconnect layer is made of a continuous element such as adhesive, and another in which the interconnect layer is made of discrete elements such as solder joints. The solutions were successfully validated with finite-element analysis, and design analyses were performed for both types of interconnect layers.      

Shock impact reliability characterization of a handheld product in accelerated tests and use environment

The effect of mechanical shock impacts is a key factor in the reliability of modern handheld products. Due to differences in product enclosures, impact orientations, strike surfaces and mountings of component boards, the loading conditions induced in a true product drop differ from those encountered in standardized board-level tests. In order to better understand the correlation between board-level drop testing and actual drops of a complete device, series of board and product-level drop tests were conducted using specialized test boards.The mechanical shock impact response of the commercial handheld device component board was characterized with the help of acoustic excitation laser vibrometry and finite element analysis. The results were used to design the mechanically compatible specialized test board for both 4-point supported board-level and unsupported product-level drop tests. Special care was taken to ensure that the vibration behavior of the test board accurately represented the vibration behavior of the commercial component board. Additional board-level drop tests were conducted using a JEDEC JESD22-B111 compliant component board for comparison.The drop test results showed that, even though the test board design and supporting method have a marked influence on the strain conditions and lifetime of solder interconnections, the primary failure mode and mechanism under the product-level drop tests is comparable to that typically encountered in the standard JEDEC JESD22-B111 board-level drop tests. More detailed analyses suggest that the comparability of the shock impact loading conditions affecting solder interconnections can be characterized using three metrics: (1) the maximum component board strain rate, (2) the maximum board strain amplitude and (3) the damping of the component board.     

Three-Dimensional Finite Element Analysis of Multiple-Grained Lead-Free Solder Interconnects

A combination of various experimental techniques was coupled with three-dimensional numerical simulation to study the strain distribution in anisotropic, heterogeneous lead (Pb)-free solder ball grid array interconnects used in electronic packages. An in situ full-field deformation map on the cross section of the joint showed a nonuniform strain distribution when the package was subjected to thermal loading. This nonuniformity was correlated with the locations of various grains on the cross section as obtained by orientation imaging microscopy (OIM) and optical microscopy. The solder interconnect was progressively sectioned and imaged under cross polarizers to discern the␣three-dimensional shapes of various grains in the solder interconnect. A methodology to replicate the three-dimensional shapes and orientations of the various grains and grain boundaries in a microstructure-based finite element model was developed. The numerical results were compared with the displacement and strain distributions obtained experimentally. The demonstrated strain localization along the grain boundaries in the case of multigrain joints and along the pad-solder interfaces in the case of the single-grain joints matched very well with the locations of plastic damage accumulation when the same interconnect was subjected to several thermal cycles.     

Effects of thermomechanical cycling on lead and lead-free (SnPb and SnAgCu) surface mount solder joints

Accelerated reliability tests have been performed on leadless and leaded lead-free and lead containing SMT component assemblies. Results so far have shown that lead-free reflow soldering is a viable alternative for conventional lead based reflow soldering. The selected ternary eutectic solder alloy SnAg3.8Cu0.7 requires higher processing temperatures which could restrict the use of certain board and component types, but other than that no major modifications seem necessary. Although better SnAg3.8Cu0.7 bulk mechanical properties were obtained compared to the near eutectic lead bearing bulk solder properties, reflowed solder joints did not reflect this difference. In general, quite similar reliability results were obtained as found for the lead based solders. Dependent on board and component metallisations and use environment, the reliability of the lead-free solders could perform better or worse than the lead based solders. Temperature dependent aspects such as solderability and mechanical behaviour of the lead-free assemblies could play a role in this. Although microstructural differences can be seen between the lead-free and lead bearing solder joints, similar joint failure mechanisms occur. Resistor solder joint cracks propagate from underneath the component through either transgranular (lead-free) grains or along intergranular (lead) grain boundaries between lead-rich and tin-rich areas and into coarsened regions near the component terminations. Gullwing lead cracks were seen propagating from the heel fillet along the lead/solder interfacial intermetallic mostly (some cracks started in the heel fillet and propagated through the solder body dispersed with coarsened spherical Ag₃Sn intermetallic particles). Package design and leadframe material seem to play a more important role in the fatigue mechanism than the change in microstructure of the solder joint.     

振动载荷下电路板级焊点失效信号表征及分析

针对板级焊点在振动载荷下的失效问题,搭建了具有焊点电信号监测功能的振动加速失效实验平台,在定频定幅简谐振动实验的基础上,对表征信号进行分析,通过电阻信号峰值标定焊点的失效程度.实验结果表明,焊点失效初期呈现为3个阶段,每个阶段包含电阻变化的平缓区间和陡变区间.随着3个阶段的改变,焊点低阻值区间振动循环数递减,焊点高阻值区间振动循环数递增.在此基础上,以电阻均值表征焊点平均失效程度,建立了表征焊点振动疲劳寿命的多项式模型,可以描述不同阶段焊点阻值和振动循环数的关系.     

High-Speed Cyclic Bend Tests and Board-Level Drop Tests for Evaluating the Robustness of Solder Joints in Printed Circuit Board Assemblies

This paper presents a comprehensive study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop impact experienced by a portable electronic product. Two test methods are used in this study: the board-level drop-shock test (BLDST) and the board-level high-speed cyclic bend test (HSCBT). The performance of (i) 12 material combinations consisting of six solder alloys and two pad finishes, and (ii) 11 manufacturing variations covering three vendors, two finishes, three immersion gold thicknesses, and three thermal aging conditions were investigated using these two test methods. Correlations between the two test methods were performed. Quantitative correlation and sensitivity coefficients for the failure modes and the measured characteristic parameters—number of drops to failure for BLDST and number of cycles to failure for HSCBT—were evaluated. Finally, the potential of HSCBT as a test method for material selection and for bridging board-level and product-level tests was demonstrated through generation of board strain versus number of cycles to failure (S–N) curves of solder joints for six material systems, four bending frequencies, and two test temperatures.     

Mechanical deflection system (MDS) test and methodology for PBGAsolder joint reliability

A mechanical deflection system (MDS) was developed for highly accelerated tests to evaluate the solder joint fatigue performance in printed circuit board assemblies. The MDS test system can be used for design verification and qualification tests for solder joint reliability. Cyclic twisting deformation is imposed on an assembled printed circuit board (PCB) at isothermal conditions. The MDS test technique makes a significant contribution to reducing solder joint reliability testing cycle time. Fatigue performance of the PBGA solder joints subjected to the MDS test was investigated by three-dimensional finite element modeling. The solder joint fatigue lives were computed for several different MDS test conditions     

Localized Recrystallization Induced by Subgrain Rotation in Sn-3.0Ag-0.5Cu Ball Grid Array Solder Interconnects During Thermal Cycling

The evolution of microstructures and grain orientations of a Pb-free solder interconnect during thermal cycling significantly affects its mechanical properties and failure modes. Thus, Sn-3.0Ag-0.5Cu ball grid array assemblies were subjected to thermal cycling to study the thermomechanical responses of the solder interconnects. The orientations and microstructures of the solder interconnects were studied by optical microscopy with cross-polarized light and scanning electron microscopy with an electron backscattered diffraction analysis system. Localized recrystallization behavior was observed in Pb-free solder interconnects during thermal cycling. Closer examination of the very early stage of recrystallization in the same solder interconnect revealed that the subgrains appeared before the formation of the recrystallized grains, and the orientations of the small recrystallized grains separated by high-angle grain boundaries evolved from the initial orientations by subgrain rotation. The localized recrystallization produced fine-grained microstructures during thermal cycling, providing an additional deformation mechanism for the solder interconnects, i.e., grain boundary sliding, which would have been impossible prior to recrystallization. The grain orientation has a strong effect on damage generation and the subsequent failure mode; initiation and propagation of cracks could be facilitated by the intrinsic anisotropic thermomechanical responses of the differently oriented grains, leading to a change in the crack propagation path and corresponding failure mode.     

Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L₁₈ orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked.     

Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact

Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability.     

A novel accelerated test technique for assessment of mechanical reliability of solder interconnects

New generations of lead-free solder interconnects are widely used in consumer electronics. Reliability of the devices which are subjected to rough handling, depends on the fracture resistance of the solder interconnects to shock and mechanical loading. The conventional reliability testing procedures are reported to be expensive and time consuming. Thus alternative tests and evaluation methods for reliability assessment of solder joints are required. In this study a new method for quality assessment of solder interconnects under high strain vibrational shear loading is presented using an ultrasonic fatigue testing system in combination with a special experimental set-up. Using this technique lifetime curves for solder ball bonds of two different Sn–Ag–Cu lead-free alloys were obtained. Failure mechanisms of the solder ball bonds were studied using SEM methods and the reliability curves were discussed with regard to the failure modes and the composition of the lead-free alloys. The applicability of the proposed method is discussed with regard to the literature data.     

Effects of solder alloy constitutive relationships on impact force responses of package-level solder joints under ball impact test

The ball impact test was developed as a package-level measure for the board-level drop reliability of solder joints in the sense that it leads to fracturing of solder joints around intermetallics, similar to that from a board-level drop test. We investigated numerically the effects of constitutive relationships of solder alloy on transient structural responses of a single package-level solder joint subjected to ball impact testing. This study focused on the characteristics of the ascending part of the impact force profile. According to the piecewise linear stress-strain curve obtained for the Sn-4Ag-0.5Cu solder alloy, parametric studies were performed by varying either segmental moduli or characteristic stresses of the curve at fixed ratios, with regard to the lack of available rate-dependent material properties of solder alloys.     

A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages

As handheld electronic products are more prone to being dropped during useful life, package-to-board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of chip-scale packages (CSPs) while mounted on printed wiring boards using board-level drop testing. Although a new board-level test method has been standardized through JEDEC (JESD22-B111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a relative prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include moldcap thickness, ball pad opening, and land grid array (LGA) versus ball grid array (BGA). The same factors were tested in board level drop to further validate the prediction model. The results indicate that the drop performance can be increased by a factor of 2 or more by changing package design variables     

Soldered joints on leaded components: Development of a design tool to predict failure during temperature cycle tests

The soldered joints inside television sets are often the cause of failure during normal use. For this reason the mechanical behaviour of soldered joints was analysed. This analysis contains three new developments: Material model for solder (containing elastic, plastic and creep properties); Mechanical model describing the behaviour of a soldered joint in combination with a leaded component on a printed board; Design tool to predict the number of cycles to failure of a leaded component during a temperature cycle test. Comparison to practical temperature cycle tests showed that a reasonably accurate prediction of the number of cycles to failure can be expected.     

Random vibration reliability of BGA lead-free solder joint

Solder joint fatigue failure under vibration loading has been a great concern in microelectronic industry. High-cycle fatigue failure of lead-free solder joints has not been adequately addressed, especially under random vibration loading. This study aims to understand the lead-free solder joint behavior of BGA packages under different random vibration loadings. At first, non-contact TV Laser holography technology was adopted to conduct experimental modal analysis of the test vehicle (printed circuit board assembly) in order to understand its dynamic characteristics. Then, its first order natural frequency was used as the center frequency and narrow-band random vibration fatigue tests with different kinds of acceleration power spectral density (PSD) amplitudes were respectively carried out. Electrical continuity through each BGA package is monitored during the vibration event in order to detect the failure of package-to-board interconnects. The typical dynamic voltage histories of failed solder joints were obtained simultaneously. Thirdly, failed solder joints were cross-sectioned and metallurgical analysis was applied to investigate the failure mechanisms of BGA lead-free solder joints under random vibration loading. The results show that the failure mechanisms of BGA lead-free solder joint vary as the acceleration PSD amplitude increases. Solder joint failure locations are changed from the solder bump body of the PCB side to the solder ball neck, finally to the Ni/intermetallic compound (IMC) interface of the package side. The corresponding failure modes are also converted from ductile fracture to brittle fracture with the increase of vibration intensity.     

An experimental approach to characterize rate-dependent failure envelopes and failure site transitions in surface mount assemblies

This paper presents an experimental approach to identify the fatigue failure envelopes for solder damage in Printed Wiring Assemblies (PWAs) subjected to dynamic loading. An empirical, rate-dependent, power-law durability model, motivated by mechanistic considerations, is proposed to characterize the failure envelopes in terms of PWA flexural strain and strain rate, as damage metrics. It is further shown that there are critical combinations of these damage parameters, beyond which the failure site changes from the solder to other locations on the PWA. A case study, using a simple PWA specimen containing a single area array component, is presented to demonstrate the proposed approach. Under certain loading conditions, the failure site changes from the bulk solder to the Cu-trace/FR4 interface. The proposed durability model is shown to successfully describe the solder damage failure envelopes. The concept of a “Failure Map” is shown to provide a suitable framework to quantify the durability of the solder interconnect, determine its failure envelope, and identify the failure transition zone of the specimen. The applicability of the proposed technique for comparing the durability of different packaging styles and for developing design guidelines for PWAs subjected to dynamic loading (for example: drop) is discussed.     

Ball-grid-array solder joint model for assembly-level impact reliability prediction

It has been well established that lead-free solder underperforms conventional leaded solder in reliability under dynamic impact. Common failures observed on ball-grid-array (BGA) solder balls on chip under board level impact include bulk solder ductile failure, intermetallic (IMC) layer crack and pad-lift. In this work, a finite element modeling approach was proposed to model bulk solder ductile failure and intermetallic layer crack. The use of beam elements and connector elements to represent the bulk solders and board/component side intermetallic layers, respectively, offers the advantage of simplicity over the use of continuum elements and cohesive elements for solder joints. This approach enables the modeling of assembly level impact with significantly less computational resources. The model was verified by comparing its prediction of BGA solder reliability against actual test results in a dynamic four-point bend test. The physical tests consist of ball impact at varying heights on a board with a mounted chip, and the subsequent analysis of the failure modes of the BGA solder joints. Simulation results were in good agreement with test results. The study shows that it is feasible to model BGA solder joint ductile failure and intermetallic layer crack under impact with simple elements with reasonable accuracy.     

Numerical Investigation of Underfill Failure Due to Phase Change of Pb-Free Flip Chip Solders During Board-Level Reflow

In this paper, the effects of phase change of Pb-free flip chip solders during board-level interconnect reflow are investigated using numerical technique. Most of the current Pb-free solder candidates are based on Sn and their melting temperatures are in the range of 220 $^{circ}$ C–240 $^{circ}$ C. Thus, Pb-free flip chip solders melt again during subsequent board-level interconnect (BGA) reflow cycle. Since solder volume expands as much as 4% during the phase change from solid to liquid, the volumetric expansion of solder in a predefined volume by chip, substrate, and underfill creates serious reliability issues. One issue is the shorting between neighboring flip chip interconnects by the interjected solder through underfill crack or delaminated interfaces. The authors have observed the interjection of molten solder and the interfacial failure of underfill during solder reflow process. In this paper, a flip chip package is modeled to quantify the effect of the volumetric expansion of Pb-free solder. Three possible cases are investigated. One is without existence of micro crack and the other two are with the interfacial crack between chip and underfill and the crack through the underfill. The strain energy release rate around the crack tip calculated by the modified crack closure integral method is compared with interfacial fracture toughness. Parametric studies are carried out by changing material properties of underfill and interconnect pitch. Also, the effects of solder interconnect geometry and crack length are explored. For the case with interfacial crack, the configuration of a large bulge with small pitch is preferred for the board-level interconnect, whereas a large pitch is preferred for cracks in the mid plane of the underfill.      

Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests.