Reliability of thermally stressed rigid–flex printed circuit boards for High Density Interconnect applications

The thermal fatigue of vias in rigid–flex printed circuit boards (PCB) is considered in the paper. Dedicated printed circuit boards have been designed with different geometrical configurations (plating thickness, drilled hole diameter and PCB thickness). The PCB is made of hundreds of vias or holes which are wired by copper path to create a daisy chain. The PCB is subject to cyclic thermal loading (−55 °C, +125 °C). Electrical connectivity is recorded during tests. Cross sectioning is performed finally to characterize the loss of electrical connectivity. Fracture of plated copper, due to the thermal expansion mismatch between constituents, is shown to be responsible for the failure of the PCB. In addition to environmental tests, finite element model is developed to analyze the deformation of PCBs during thermal cycling. Areas of strain concentration determined by Finite Element Analysis (FEA) are consistent with locations where cracks were observed in experiments. In addition, the numerical estimation of the plastic strain increment per cycle enables the prediction of the fatigue life. The results confirm that for rigid flex boards, the fatigue life of vias increases with higher plating thickness, larger drilled hole size and lower PCB thickness. Numerical results are shown to be in good agreement with experiments.     

LCCC封装器件热疲劳失效分析及结构优化研究

针对LCCC封装器件在温度循环载荷下焊点开裂的问题,首先分析其失效现象和机理,并建立有限元模型,进行失效应力仿真模拟。为降低焊点由封装材料CTE不匹配引起的热应力,提出了两种印制板应力释放方案,并分析研究单孔方案中不同孔径和阵列孔方案中不同孔数量对热疲劳寿命的影响。之后,为降低对PCB布局密度的影响,提出一种新型的叠层焊柱应力缓冲方案,进行了不同叠层板厚度和焊柱间距的敏感度分析。结果表明,更大的开孔面积、更小的叠层板厚度、更密的焊柱可有效降低焊点应力,提高焊点热疲劳寿命,使得LCCC封装器件焊点热疲劳可靠性得到有效提高。     

Solder joint crack propagation analysis of wafer-level chip scalepackage on printed circuit board assemblies

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mechanics with finite element method. Furthermore, an empirical equation for predicting the thermal-fatigue life of flip chip solder joints is proposed     

Fatigue life of lead-free solder thermal interface materials at varying bond line thickness in microelectronics

Microelectronics failure during operation is commonly attributed to ineffective heat management within the system. Hence, reliability of such devices becomes a challenge area. The use of lead-free solders as thermal interface materials to improve the heat conduction between a chip level device and a heat sink is becoming popular due to their promising thermal and mechanical material properties. Finite element modelling was employed in the analysis of the fatigue life of three lead-free solders (SAC105, SAC305, and SAC405) under commercial thermal cycling load (between −40 °C and 85 °C). This paper presents the results of the simulation work focusing on the effect of varying the solder thermal interface thickness (or bond line thickness) on the reliability of the microelectronic device. The results obtained were based on stress, strain, deformation, and plastic work density. The results showed that the fatigue life of the three solders increases as the solder thermal interface thickness increases. Also, the stresses, strains, and deformation were highest around the edges and vertices of the solder interface. In addition, the optimal solder material of choice based on the criteria of this research is given as SAC405. It has higher operational life span and good reliability capabilities.     

Reliability of via-in-pad structures in mechanical cycling fatigue

Increased packaging density, along with large-scale implementation of ball grid arrays (BGAs), chip scale packages and DCAs in portable products has resulted in the need for innovative techniques to increase the I/O density in printed circuit boards. With the development of high density interconnect (HDI), via-in-pad has emerged as one of the key enabling technologies for increasing the I/O density. Via-in-pad permits the use of sub-surface layers for fan out and consequently, smaller packages with higher I/O can be utilized in the design. Additionally, since traces no longer need to be routed between pads, the solder joint pitch can also be decreased. The reliability of via-in-pad under mechanical bend fatigue is examined in this study. Mechanical cycling fatigue reliability is especially critical for portable products where keypad actuation often induces repeated bending in the printed circuit board. HDI boards manufactured by both the photovia and the laser via processes were examined. A three dimensional, non-linear, parametric finite element model was developed to predict failure mechanisms. For the bend fatigue experiments, globtop BGA packages were mounted on HDI boards containing via-in-pad structures. The number of cycles required for material fatigue was obtained as a function of applied bending loads. Failure analysis was conducted to determine the failure modes. Experimental results were correlated with finite element predictions.     

Computational parametric analyzes on the solder joint reliability of bottom leaded plastic (BLP) package

The bottom-leaded plastic (BLP) package is a lead-on-chip type of chip scale package (CSP) developed mainly for memory devices. Because the BLP package is one of the smallest plastic packages available, solder joint reliability becomes a critical issue. In this study, a 28-pin BLP package is modeled to investigate the effects of molding compound and leadframe material properties, the thickness of printed circuit board (PCB), the shape of solder joint and the solder pad size on the board level solder joint reliability. A viscoplastic constitutive relation is adopted for the modeling of solder in order to account for its time and temperature dependence on thermal cycling. A three-dimensional nonlinear finite element analysis based on the above constitutive relation is conducted to model the response of a BLP assembly subjected to thermal cycling. The fatigue life of the solder joint is estimated by the modified Coffin-Manson equation. The two coefficients in the modified Coffin-Manson equation are also determined. Parametric studies are performed to investigate the dependence of solder joint fatigue life on various design factors.     

Analytical modeling of thermal stresses in plated through via (PTV) structures

Plated through via (PTV) structures are widely used in printed circuit boards for interconnect. Due to the mismatch in the coefficient of thermal expansion (CTE) between the PTV and the board material, high thermal stresses can be induced in the PTV during high temperature soldering and normal usage. In particular, PTVs can fail due to cyclic temperature changes which cause thermal fatigue. This paper describes an analytical model of the thermal stresses in PTV structures using variational mechanics. Stress components are compared with those obtained using finite element analysis and with another analytical model.     

Design methodologies for reliability of SSL LED boards

This work presents a comparison of various LED board technologies from thermal, mechanical and reliability point of view provided by an accurate 3-D modelling. LED boards are proposed as a possible technology replacement of FR4 LED boards used in 400 lumen retrofit SSL lamps. Presented design methodology can be used for other high power SSL lamp designs. The performance of new LED board designs were evaluated by numerical modeling. Modeling methodology was proven by measurement on reference FR4 LED board. Thermal performance was compared by extracting of LED boards thermal resistances and thermal stress has been inspected considering the widest temperature operating range according to standards (−40 to +125 °C). Thermo-mechanical and reliability analysis have been performed to study parameters of each LED board technology, using thermal boundary conditions extracted from the thermal simulation of a whole LED lamp. Elastic–plastic analysis with temperature dependent stress–strain material properties has been performed. The objective of the work is to optimize not only the thermal management by thermal simulation of LED boards, but also to find potential problems from mechanical failure point of view and to present a methodology to design SSL LED boards for reliability.     

Prognostics implementation of electronics under vibration loading

In this paper, a methodology is developed for monitoring, recording, and analyzing the life-cycle vibration loads for remaining-life prognostics of electronics. The responses of printed circuit boards to vibration loading in terms of bending curvature are monitored using strain gauges. An analytical model calibrated by finite element analysis is developed to calculate the strain at interconnects using the measured response. The interconnect strain values are then used in a vibration failure fatigue model for damage assessment. Damage estimates are accumulated using Miner’s rule after every mission and then used to predict the life consumed and remaining-life. The methodology has been demonstrated for remaining-life prognostics of a printed circuit board. The result has also been verified by the real-time to failure of the components by checking the components’ resistance data.     

Joint reliability evaluation of thermo-compression bonded FPCB/RPCB joints under high temperature storage test

In this study, electrodes on a flexible printed circuit board (FPCB) and rigid printed circuit board (RPCB) were bonded by a thermo-compression bonding. Pb-free Sn–3.0Ag–0.5Cu solder was used as an interlayer. In order to determine the optimum bonding conditions for bonding pressure and time, a 90° peel test of the FPCB–RPCB joint was conducted. The relationships between the bonding conditions, interfacial reactions, and peel strength were investigated. The optimum bonding pressure and time were 2.04 MPa and 5 s at 260 °C, respectively. Thin and uniform (Ni,Cu)₃Sn₄ intermetallic compound (IMC) layers formed at both FPCB/Sn–3.0Ag–0.5Cu/RPCB interfaces. In a high temperature storage (HTS) test of 125 °C, the peel strength decreased as the aging time increased. After the HTS test, brittle interfaces formed in the PCB joints, resulting in the switching of the failure mode from a polyimide–electrode failure to a brittle IMC failure.     

Highly reliable, fine pitch chip on glass (COG) joints fabricated using Sn/Cu bumps and non-conductive adhesives

We have developed a reliable and ultra-fine pitch chip on glass (COG) bonding technique using Sn/Cu bumps and non-conductive adhesive (NCA). Sn/Cu bumps were formed by electroplating and reflowed, forming dome shaped Sn bumps on Cu columns. COG bonding was performed between the reflowed Sn/Cu bumps on the oxidized Si wafer and ITO/Au/Cu/Ti/glass substrate using a thermo-compression bonder. Three different NCAs were applied during bonding. Bonding temperature was 150 °C for NCA-A and NCA-B, and 110 °C for NCA-C. The electrical properties of COG joints were evaluated by measuring the contact resistance of each joint through the four-point probe method. All joints were successfully bonded and the electrical measurement showed that the average contact resistance of each joint was approximately 30 mΩ, regardless of NCA types. The COG joints were subjected to a series of reliability tests: high temperature storage test (85 °C, 160 h); thermal cycling test (−40 °C/+85 °C, 20 cycle); and a temperature and humidity test (50 °C/90%, 160 h) were sequentially performed to evaluate the reliability of the COG joints. The contact resistance measurement showed that there were no failed bumps in all specimens and all joints passed the criterion after reliability test.     

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (ΔT) effects on the predicted fatigue lives of solder joints are reported     

印刷电路板温度-应力耦合场有限元分析

温度和热应力是引起印刷电路板功能失效的重要原因,针对某电子设备的PCB。对其温度-应力耦合场进行有限元分析,找出了印刷电路最大可能的失效区域;采用DOE方法对元器件结构布局进行了优化设计,使离面正负最大变形量达到最小值,应力集中得到了改善,提高了PCB的使用寿命。     

Predictive modeling of board level shock-impact reliability of the HVQFN-family

A semi-empirical model is derived to predict the board level drop-impact lifetime of HVQFN-packages soldered on a printed circuit board. The strain that evolves in the soldered interconnections is evaluated by a finite element model and related to the experimentally determined lifetime. The result is a power law and it is compared to literature data. In addition, a measure for the strain on the board is obtained analytically and compared with the experimental data. Here, too, dependence in the form of a power law is found. The combination of both results strongly suggests a near-linear relationship between the strain in the solder and the strain in the board.     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

Mechanical cycling fatigue of PBGA package interconnects

Increased packaging density in micro-electronic products has advantaged attach of BGA, micro-BGA, CSP, and DCA packages. These area array packages are assembled to circuit boards that are reduced in size and thickness, by necessity. These assemblies would include flexible thin laminate circuit boards with area array components attached by solder balls. In normal use, these assemblies would be subjected to numerous ultra-low frequency mechanical deflections; consider a keypad when the user enters telephone numbers. Most of the reliability studies of area array packages have dealt with temperature cycling induced fatigue. However, less attention has been paid to mechanical bending fatigue of these packages.A test method has been developed to elucidate the mechanical bending fatigue issues of BGA, micro-BGA, CSP, and DCA packages attached to printed circuit boards. Appropriate bending fatigue reliability models and their theoretical basis are being developed. The test method and preliminary mechanical cyclic fatigue data on a PBGA package will be presented as a function of printed circuit board thickness. Consideration will be given to fatigue fracture morphology and its relation to solder joint location and rate of crack growth.     

A new experimental method to evaluate creep fatigue life of flip-chip solder joints with underfill

A new accelerated stress test method was developed to evaluate creep life of flip-chip solder joints with underfill. With this method, a cyclic creep test can be done simply by applying a displacement to the FR-4 printed circuit board (PCB) board in the axial direction. The creep fatigue test was performed under displacement control with real-time electrical continuity monitoring. Test results show that the displacement arising from the force is equivalent to the thermal stress during thermal expansion. It was found that the magnitude of displacement was proportional to the inelastic strain sustained by the solder joints. This indicates that the creep fatigue life obtained will not only reflect the quality of the solder joints, but can also be used to characterize the reliability of the flip-chip assembly. Finite element modeling was also performed to confirm the agreement of deformation of the solder joints under mechanical and thermal loading. Results suggest that deformation and strain of the flip-chip assembly are consistent or comparable between the mechanical and thermal cycling. The failure analysis indicates that fatigue cracks often initiate from the top edge of a corner solder joint in the creep fatigue test, which is similar to what would happen in thermal cycling test. Lastly, the effect of underfill on the creep fatigue test is discussed. It is postulated that the test method is applicable to other flip-chip assemblies, such as conductive adhesive interconnections.     

An investigation of Sn pest in pure Sn and Sn-based solders

Five solders Sn-0.7Cu, Sn-3.4Ag-0.8Cu, Sn-3.5Ag, Sn-36Pb-2Ag, and pure Sn, and two mobile phone boards were tested at low temperatures for tin pest. The samples were stored at −196 °C for 50 h, −40 °C for 4 years, and finally −17 °C for 1.5 years. Tin pest was observed in pure tin but not in any of the solder alloys or the boards tested. It is suggested that the mechanical properties of tin-based solders play a key role in tin pest formation. Any factor that strengthens the materials can increase the resistance to tin pest. Influential factors such as solder composition, test temperature, and types of alloys are discussed.     

Low cost solar irradiation sensor and its thermal behaviour

This paper presents the working principle, design and thermal characterization of an irradiation sensor. The irradiation measurement device must have accuracy and a reliable construction under outdoor use conditions. The sensor is based on a photoelectric cell and incorporates a read-out circuit for providing steady short circuit conditions for the cell as well as for signal amplification. Thermal tests (HTS, LTOL) were accomplished in a climate chamber in the temperature range of −20 to 80 °C in steps of 10 °C. To determine the fundamentals of the thermal dependence of the sensor cell spectral response measurements under varying temperatures were performed. Measurements show that the self-made solar cell’s thermal dependence was 0.26% °C⁻¹, revealing higher temperature dependence than in the case of an industrial reference cell.     

A strategy for damage assessment of thermally stressed copper vias in microelectronic printed circuit boards

The thermal fatigue of plated-through vias remains a subject of concern, particularly when exposed to the high operating temperatures associated with automotive applications. In this paper the performance of different types of copper vias in different positions of a printed circuit board is analyzed. To this end a two-scale finite element analysis under the loading conditions of thermal cycling is employed. A new material model for the electrolytically deposited copper accounts for large elastic and plastic deformations and, additionally, for the growth of pores within the material.It is common practice to extrapolate the plastic straining computed within few steps of thermal cycling by means of a Coffin–Manson-Equation. We critical examine this strategy and point out, that a certain number of about 20 cycling steps is necessary to obtain meaningful extrapolations. Furthermore, an extrapolation of the computed porosity up to critical values allows similar conclusions.The presented strategy can serve as a predictive tool for plated through holes and vias and can reduce the need of repetitive experimental failure tests.