Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network

In this paper, a CMOS low-noise amplifier (LNA) with a new input matching topology has been proposed, analyzed and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NF_min of 4.46 dB. The reverse isolation S12 of the LNA can achieve and the input and output return losses are better than . The input 1-dB compression point is and IIP3 is . This LNA drains 10 mA from the supply voltage of 1 V.     

CMOS低噪声放大器中的输入匹配研究与设计

分析了低噪声放大器设计中最常用的源极电感负反馈输入匹配结构,指出其存在的缺陷及如何改进,即利用一个小值LC网络代替大感值的栅极电感Lg,同时移除源极负反馈电感Ls.应用这种改进型输入匹配结构,基于0.18μm BSIM3模型设计了工作频带为5.1～5.8 GHz的宽带CMOS低噪声放大器.结果表明,虽然输入匹配由于移除源极负反馈电感Ls受到一定影响,但是有利于降低噪声系数并减小实际制作的芯片面积.     

低功耗高增益CMOS LNA的设计

设计了一种完全可以单片集成的低功耗高增益CMOS低噪声放大器(LNA).所有电感都采用片上螺旋电感,并实现了片上50 Ω的输入阻抗匹配.文中设计的放大器采用TSMC0.18 μmCMOS工艺,用HSPICE模拟软件对其进行了仿真,并进行了流片测试.结果表明,所设计的低噪声放大器结构简单,极限尺寸为0.18 μm,当中心频率fo为2.4 GHz、电源电压VDD为1.8 V时其功率增益S21为16.5 dB,但功耗Pd只有2.9 mW,噪声系数NF为2.4 dB,反向隔离度S12为-58 dB.由此验证了所设计的CMOS RF放大器可以在满足低噪声、低功耗、高增益的前提下向100 nm级的研发方向发展.     

Linearity improvement of cascode low-noise amplifiers using double DS method with a tuned inductor

We propose a highly linear low-noise amplifier (LNA) using the double derivative superposition method with a tuned inductor. This topology has an auxiliary common gate stage of the cascode amplifier to cancel each third-order intermodulation distortion (IMD3) component and can provide a high third-order input intercept point (IIP3) for the 5.25 GHz frequency band. From the simulation results using the TSMC 0.18 μm RF CMOS process, the IIP3 in the proposed cascode LNAs can be improved by 9 dB, compared with the conventional derivative superposition method. The proposed LNA achieves an IIP3 of + 15 dBm with a gain of 10.5 dB, a noise figure of 2.4 dB, and a power consumption of 6 mA at 1.5 V.     

一个具有前置低噪放的宽动态范围线性RF功率检测器

摘要：本文给出了一个针对发射机载波泄露抑制的宽动态范围线性射频功率检测器的设计。该检测器基于对数放大器原理,并运用逐级检测的方法在射频频段实现宽动态范围。为提高灵敏度,检测器前端放置了一个低噪声放大器。而出于减小寄生和面积的目的,检测器采用直流耦合的架构,但这将导致电路中的直流失调对其动态范围形成危害。因此,本文提出一个直流失调消除技术用于消除检测器的直流失调。最终,检测器采用SMIC 0.13μm CMOS 工艺流片,测试结果表明其在900MHz/2GHz,分别实现了50dB/40dB的宽动态范围且检测误差在?1dB之内,功耗为16mA?1.5V。面积为0.27?0.67mm2。     

Design of low power UWB LNA based on common source topology with current-reused technique

This paper presents two low power UWB LNAs with common source topology. The power reduction is achieved by the current-reused technique. The gain and noise enhancement of the proposed circuit is based on an output buffer which is used by a common source amplifier with shunt–shunt feedback. Chip1 is an adopted T-match input network of 50 Ω matching in the required band. Measurements show that the S₁₁ and S₂₂ are less than −10 dB, and the maximum amplifier gain S₂₁ gives 9.7 dB, and the noise figure is 4.2 dB, the IIP3 is −8.5 dBm, and the power consumption is 11 mW from 1.1 V supply voltage. The input matching of chip2 is adopted from a LC high pass filter and source degenerated inductor. The output buffer with the RC-feedback topology can improve the gain, increase the IIP3, restrain the noise, improve the noise figure and decrease the DC power dissipation. Measurements show 13.2 dB of power gain, 3.33 dB of noise figure, and the IIP3 is −3.3 dBm. It consumes 9.3 mW from 1.5 V supply voltage. These two chips are implemented in a 0.18 μm TSMC CMOS process.     

LTE 毫微微蜂窝基站射频收发器的设计与实现*

针对近年来LTE 毫微微蜂窝基站商用加快和规模扩大,减小LTE 毫微微蜂窝基站的尺寸和降低其成 本就变得越来越重要。在保证基站性能的基础上,如何设计无线电收发器以减少尺寸和成本成为很大的挑战。设 计了一种应用于LTE 毫微微蜂窝基站中的低成本MIMO 射频收发器。分析了发射机和接收机的各项需求指标,提 出了块级的射频参数。据此,射频收发器被系统地分为几个子模块,分别设计了这些不同的子模块,同时区分各个 子模块的特点。所得到的测定结果表明,充分集成的射频收发器的设计不仅具有小尺寸,也符合LTE 毫微微基站的 各项指标。     

记忆性接收系统的非线性失真分析

在一般只讨论系统幅度非线性失真文献的基础上,推导给出了是否考虑系统记忆特性的依据,重点分析了各失真分量对系统性能的影响并探讨了同频寄生分量输出的双重属性,最后澄清了关于三阶截点的模糊认识。