A source-line programming scheme for low-voltage operation NANDflash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme     

Pulsed tunnel programming of nonvolatile memories

This paper investigates the use of Fowler-Nordheim tunneling for Flash memories programming looking for a good tradeoff between applied voltage (to relax requirements for on-chip circuitry), program time and oxide stress-induced leakage current (SILC) degradation. Exploiting the results of a recent study of trap dynamics under pulsed tunnel conditions, it is shown that by means of a small number of relatively high voltage pulses, memories featuring oxide thickness of 7 nm can be programmed in about 20 /spl mu/s with smaller SILC degradation than commonly achieved with programming times in the ms range.     

A standby current limited performance figure of merit for deepsub-micron CMOS

The delay time of an inverter or NAND chain at a gate length yielding equal standby current and active current is used as the definition of a maximum Figure of Merit (FOM), FOM_max. The circuit power that occurs under this condition of equal standby and active currents is an equally important measure. This FOM_max technique is particularly useful in characterizing complementary metal-oxide-semiconductor (CMOS) technologies in the deep submicron regime. A knowledge of the exact value of gate length is not necessary to apply the FOM_max methodology. For a fixed supply voltage and gate oxide thickness, node capacitance and transistor drive, and off currents determine the value of FOM_max. The value of gate length at which FOM_max occurs decreases with decreasing supply voltage. FOM_max analysis is applied to the comparison of CMOS technologies using gate oxide thicknesses of 5.7 and 3.8 nm     

Low Voltage Flash Memory Cells Using SiGe Quantum Dots for Enhancing F-N Tunneling

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

基于SiGe量子点实现增强F-N隧穿的低压闪速存储器

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

Voltage-Dependent Charge Storage in Cladded Zn0.56Cd0.44Se Quantum Dot MOS Capacitors for Multibit Memory Applications

As conventional memories approach scaling limitations, new storage methods must be utilized to increase Si yield and produce higher on-chip memory density. Use of II–VI Zn_0.56Cd_0.44Se quantum dots (QDs) is compatible with epitaxial gate insulators such as ZnS-ZnMgS. Voltage-dependent charging effects in cladded Zn_0.56Cd_0.44Se QDs are presented in a conventional metal–oxide–semiconductor capacitor structure. Charge storage capabilities in Si and ZnMgS QDs have been reported by various researchers; this work is focused on II–VI material Zn_0.56Cd_0.44Se QDs nucleated using photoassisted microwave plasma metalorganic chemical vapor deposition. Using capacitance–voltage hysteresis characterization, the multistep charging and discharging capabilities of the QDs at room temperature are presented. Three charging states are presented within a 10 V charging voltage range. These characteristics exemplify discrete charge states in the QD layer, perfect for multibit, QD-functionalized high-density memory applications. Multiple charge states with low operating voltage provide device characteristics that can be used for multibit storage by allowing varying charges to be stored in a QD layer based on the applied “write” voltage.     

A 1.0 V power supply, 9.3 GB/s write speed, Single-Cell Self-Boost program scheme for high performance ferroelectric NAND flash SSD

A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0 V power supply operation in Ferroelectric (Fe-) NAND flash memories. The proposed SCSB scheme only self-boosts the channel voltage of the cell to which the program voltage V_PGM is applied in the program-inhibit NAND string. The program disturb is well suppressed at the 1.0 V power supply voltage in the proposed program scheme. The power consumption of the Fe-NAND at V_CC = 1.0 V decreases by 86% compared with the conventional floating gate (FG-) NAND at V_CC = 1.8 V without the degradation of the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.7 times and the 9.3 GB/s write throughput of the Fe-NAND SSD is achieved for an enterprise application.     

大容量NAND Flash K9T1G08UOM在网络存储中的应用

针对嵌入式系统对存储的需求，提出了基于大容量NAND Flash的存储方案。简要介绍NAND Flash器件K9T1G08UOM及其编程特点，并讨论了网络存储应用的存储策略和数据可靠性方面的考虑，设计并实现了网络数据流的NAND Flash存储。     

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current     

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

SILC dynamics in MOS structures subject to periodic stress

This work investigates stress-induced leakage current (SILC) in thin-oxide MOS capacitors subject to (quasiperiodic) ac voltage stress, under the condition of fixed charge fluence through the oxide. It shows that both trap creation and spontaneous trap annealing play a significant role when the duration of, and the time between, high-voltage pulses are comparable with characteristic times of trap dynamics. A phenomenological model is introduced that is able to accurately represent the main physical phenomena due to pulsed voltage stress under conditions of interest for unconventional programming schemes for fast programming nonvolatile memories (NVMs) with acceptable oxide degradation.     

A 144-Mb, eight-level NAND flash memory with optimized pulsewidthprogramming

We report a fast-programming, compact sense and latch (SL) circuit to realize an eight-level NAND flash memory. Fast programming is achieved by supplying optimized voltage and pulsewidth to the bit lines, according to the programming data. As a result, all data programming is completed almost simultaneously, and 0.67-MB/s program throughput, which is 1.7 times faster than conventional program throughput, is achieved. The compact layout of the SL circuit is made possible by four 3-bit latches sharing one unit of the read/verify control circuit. Using these techniques, we fabricated a 144-Mb, eight-level NAND flash memory using a 0.35-μm CMOS process, resulting in a 104.2-mm² die size and a 1.05-μm² effective cell size     

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL voltage modulated ISPP scheme was used as parallel MSB programming in order to reduce cell-to-cell interference caused by the order in which the cells are programmed. By adopting the proposed page architecture, the number of neighbor cells that are programmed after programming a selected cell in BL direction as well as their amount of T/th shift during programming can be suppressed largely without increasing memory array size. Compared to conventional architecture it leads to a reduction of BL-BL cell-to-cell interference by almost 100%, and of WL-WL and diagonal cell-to-cell interferences by 50% at the 60 nm technology node. The proposed architecture enables also to improve average MLC program speed performance by 11% compared with conventional architecture, thanks to its fast LSB program performance.     

A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS NAND flash application

A novel channel-program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture for the first time [Hsu TH, Wu JY, King YC, Lue HT, Shih YH, Lai EK, et al. A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS memory application. In: Tech digest 2006 European solid-state device research conference (ESSDERC); 2006. p. 222–5], [1]. The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot-hole (STHH) injection for programming and erasing, respectively. Gate bias polarity serves to control whether hot electrons or hot holes are injected into the nitride storage layer. More efficient program and erase operations are achieved compared to the conventional Fowler–Nordheim (FN) tunneling method. The new technique operates at lower programming voltages and with shorter duration pulses, thus increases the programming throughput. Moreover, good program/erase disturb immunity, cycling endurance and data retention are demonstrated.     

All-optical NAND gate using integrated SOA-based Mach–Zehnder interferometer

An all-optical NAND gate using integrated SOA-based Mach–Zehnder interferometer is proposed and demonstrated for the first time. Numerical analysis shows the switching window of the proposed NAND gate, which is synchronous with the dynamic gain experienced by the probe pulses. The effects of the SOA and input data parameters on the switching performance are discussed. The operation of the proposed NAND gate with 10 Gb/s RZ pseudorandom bit sequences is simulated and the results demonstrate its effectiveness. This NAND gate could provide a new possibility for all-optical routing in future all-optical networks.     

Fast tunneling programming of nonvolatile memories

This work investigates the possibility of programming nonvolatile memories in the ns time scale, for possible replacement of DRAMs, at least in special applications where low-power requirements do not allow frequent data refreshing. The study demonstrates the possibility of using high voltage tunneling pulses to achieve program times significantly shorter than 100 ns with acceptable oxide damage     

High-Voltage Analog System for a Mobile NAND Flash

High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memory in a mobile handset. Regulated high voltage generation at low supply voltage is achieved with optimized oscillator, high-voltage charge pump, and voltage regulator circuits. We developed a design methodology for a high-voltage charge pump to minimize silicon area, noise, and power consumption of the circuit without degrading the high-voltage output drive capability. Novel circuit techniques are proposed for low supply voltage operation. Both the oscillator and the regulator circuits achieve 1.5 V operation, while the regulator includes a ripple suppression circuit that is simple and robust. Through the paper, theoretical analysis of the proposed circuits is provided along with Spice simulations. A mobile NAND Flash device is realized with an advanced 63 nm technology to verify the operation of the proposed circuits. Extensive measurements show agreement with the results predicted by both analysis and simulation.     

一种用于NAND闪存的奇偶位线块编程补偿算法

为改善数据保持干扰和编程干扰对NAND闪存可靠性的影响,提出了一种新的奇偶位线块编程补偿算法。该算法利用编程干扰效应来补偿由数据保持引起的阈值漂移,修复NAND闪存因数据保持产生的误码,提高了NAND闪存的可靠性。将该算法应用于编程擦除次数为3k次的1x-nm MLC NAND闪存。实验结果表明,在数据保持时间为1年的条件下,与传统奇偶交叉编程算法相比,采用该补偿算法的NAND闪存的误码降低了93%;与读串扰恢复算法相比,采用该补偿算法的NAND闪存的误码下降了38%。     

Scaling of multidielectric nonvolatile SONOS memory structures

Present-day low-power, portable lap-top computers and consumer products require non-volatile semiconductor memory (NVSM) operating at 5 V with a trend towards reducing this level to 3.3 V. The SONOS technology, an acronym for the polySilicon-blocking Oxide-Nitride-tunnel Oxide-Silicon structure used in capacitors and transistors, shows promise as a technology for present and future low voltage NVSM applications. The nitride layer in the dielectric sandwich permits the storage of charge resulting in adjustable threshold voltages. This paper examines the physics and characterization of scaled SONOS NVSM transistors in relation to reducing the programming voltage. We develop a model for the transient characteristics of the SONOS NVSM transistor with: (1) a simple closed-form solution valid for short programming times; and (2) a numerical solution covering the entire range of programming times. The simple closed-form solution clearly illustrates the dependence of the turn-on time and erase/white slope on the dielectric thicknesses, initial stored charge in the nitride, and programming voltage. In particular, we have examined: (1) decreasing the tunnel oxide thickness; and (2) scaling the blocking oxide thickness. By properly scaling the dielectric films (11 Å tunnel oxide, 50 Å nitride, 40 Å blocking oxide), a ±8 V programmable SONOS device has been obtained with a 50 μs write time and a 100 μs erase time for a 3 V memory window, and a ±5 V programmable device with a 100 ms erase and write time for a 1.5 V memory window.     

A statistical methodology as applied to a 256 Mbit DRAM passtransistor design

We present a novel design for manufacturing (DFM) methodology that has been applied to the design of a pass transistor for 256 Mbit DRAM. The design inputs that include gate oxide thickness, which limits the booted wordline voltage, the threshold voltage adjust implant, and the substrate bias voltage, for different channel lengths, are optimized to meet the constraints on performance, reliability, and robustness against manufacturing variations. The problems associated with applying conventional DFM techniques are discussed and a new methodology based on “margins” is presented. The results pertaining to the optimized DRAM pass transistor design for a power supply voltage V_cc=2.5 V are presented,