Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

The current-voltage-temperature characteristics of Al/NPB/p-Si contact

The current-voltage (I-V) characteristics of the Al/NPB/p-Si contact shows rectifying behavior with a potential barrier formed at the contact interface. The barrier height and ideality factor values of 0.65 eV and 1.33 are measured at the forward bias of the diode. The barrier height of the Al/NPB/p-Si diode at room temperature is larger that (∼0.58 eV) of conventional Al/p-Si diode. It reveals the NPB organic film control the carrier transport of the diode at the contact interface. The temperature effect on the I-V measurement is also performed to reveal the junction characteristics. The ideality factor of the Al/NPB/p-Si contact increases with decreasing temperature. And the barrier height decreases with decreasing temperature. The effects are due to the existence of the interface states and the inhomogeneous of the barrier at the junction.     

The effects of 12 MeV electron irradiation on the electrical characteristics of the Au/Aniline blue/p-Si/Al device

An Au/Aniline blue (AB)/p-Si/Al structure has been fabricated and then the effect of electron irradiation (12 MeV electron energy and 5 × 10¹² e⁻ cm⁻² fluence) on the contact parameters of the device has been analysed by using the current-voltage (I-V), capacitance-voltage (C-V), and conductance-voltage (G/w-V) measurements, at room temperature. Since the organic layer creates a physical barrier between the metal and the semiconductor, it has been seen that the AB layer causes an increase in the effective barrier height of the device. Cheung functions, Norde model and conductance method have been used in order to determine the diode parameters. The values of the ideality factor, barrier height and series resistance increased after the electron irradiation. This has been attributed to a decrease in the net ionized dopant concentration that occurred as a result of electron irradiation.     

Calculation from the current-voltage and capacitance-voltage measurements of characteristics parameters of Cd/CdS/n-Si/Au-Sb structure with CdS interface layer grown on n-Si substrate by SILAR method

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au-Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au-Sb structure has demonstrated clearly rectifying behaviour by the current-voltage (I-V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au-Sb structure have been calculated from the forward bias I-V and reverse bias C⁻²-V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φ_b = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I-V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (R_s) effect has been observed. The values of R_s obtained from dV/d(lnI)-I and H(I)-I plots are near to each others (R_s = 182.24 Ω and R_s = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C⁻² -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (N_ss) of the device has been obtained from the forward bias I-V characteristics. It has been seen that, the N_ss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.     

Effect of rapid thermal annealing on deep level defects in the Si-doped GaN

Rapid thermal annealing effects on deep level defects in the n-type GaN layer grown by metalorganic chemical vapor deposition (MOCVD) have been characterized using deep level transient spectroscopy (DLTS) technique. The samples were first characterized by current-voltage (I-V) and capacitance-voltage (C-V) measurements. The measurements showed that the barrier height of the as-grown sample to be 0.74 eV (I-V) and 0.95 eV (C-V) respectively. However, the Schottky barrier height of the sample annealed at 800 °C increased to 0.84 eV (I-V) and 0.99 eV (C-V) respectively in nitrogen atmosphere for 1 min. Further, it was observed that the Schottky barrier height slightly decreased after annealing at 900 °C. DLTS results showed that the two deep levels are identified in as-grown sample (E1 and E3), which have activation energies of 0.19 ± 0.01 eV and 0.80 ± 0.01 eV with capture cross-sections 2.06 × 10⁻¹⁷ cm² and 7.68 × 10⁻¹⁸ cm², which can be related to point defects. After annealing at 700 °C, the appearance of one new peak (E2) at activation energy of 0.49 ± 0.02 eV with capture-cross section σ_n = 5.43 × 10⁻¹⁷ cm², suggest that E2 level is most probably associated with the nitrogen antisites. Thermal annealing at 800 °C caused the E1 and E3 levels to be annealed out, which suggest that they are most probably associated with the point defects. After annealing at 900 °C the same (E1 and E3) deep levels are identified, which were identified in as-grown n-GaN layer.     

Fabrication and characterization of p-n junctions based on ZnO and CuPc

p-n Junctions based on zinc oxide (ZnO) and copper-phthalocyanine (CuPc) were fabricated using pulsed laser deposition and thermal evaporator techniques, respectively. Current-voltage (I-V) characteristics of the ZnO-CuPc junction showed rectifying behavior. Various junction parameters such as barrier height and ideality factor were calculated using I-V data and observed to be 0.63 ± 0.02 eV and 4.0 ± 0.3, respectively. Cheung and Norde’s method were used to compare the junction parameters obtained by I-V characteristics.     

The electrical characteristics of Sn/methyl-red/p-type Si/Al contacts

The junction characteristics of the organic compound methyl-red film (2-[4-(dimethylamino)phenylazo]benzoic acid) on a p-type Si substrate have been studied. The current-voltage characteristics of the device have rectifying behavior with a potential barrier formed at the interface. The barrier height and ideality factor values of 0.73 eV and 3.22 for the structure have been obtained from the forward bias current-voltage (I-V) characteristics. The interface state energy distribution and their relaxation time have ranged from 1.68 × 10¹² cm⁻² eV⁻¹ and 1.68 × 10⁻³ s in (0.73-E_v) eV to 1.80 × 10¹² cm⁻² eV⁻¹ and 5.29 × 10⁻⁵ s in (0.43-E_v) eV, respectively, from the forward bias capacitance-frequency and conductance-frequency characteristics. Furthermore, the relaxation time of the interface states shows an exponential rise with bias from (0.43-E_v) eV towards (0.73-E_v) eV.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

Electrical characteristics and inhomogeneous barrier analysis of Au-Be/p-InSe:Cd Schottky barrier diodes

We have identically prepared Au-Be/p-InSe:Cd Schottky barrier diodes (SBDs) (21 dots) on the InSe:Cd substrate. The electrical analysis of Au-Be/p-InSe:Cd structure has been investigated by means of current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) measurements at 296 K temperature in dark conditions. The effective barrier heights and ideality factors of identically fabricated Au-Be/p-InSe:Cd SBDs have been calculated from their experimental forward bias current-voltage (I-V) characteristics by applying a thermionic emission theory. The BH values obtained from the I-V characteristics have varied between 0.74 eV and 0.82 eV with values of ideality factors ranging between 1.49 and 1.11 for the Au-Be/p-InSe:Cd SBDs. It has been determined a lateral homogeneous barrier height value of approximately 0.82 eV for these structures from the experimental linear relationship between barrier heights and ideality factors. The Schottky barrier height (SBH) value has been obtained from the reverse-bias C-V characteristics of Au-Be/p-InSe:Cd SBD for only one diode. At high currents in the forward direction, the series resistance effect has been observed. The value of series resistance has been determined from I-V measurements using Cheung’s and Norde’s methods.     

Characterization of current-voltage (I-V) and capacitance-voltage-frequency (C-V-f) features of Al/SiO2/p-Si (MIS) Schottky diodes

The current-voltage (I-V) characteristics of metal-insulator-semiconductor Al/SiO₂/p-Si (MIS) Schottky diodes were measured at room temperature (300 K). In addition, capacitance-voltage-frequency (C-V-f) characteristics are investigated by considering the interface states (N_ss) at frequency range 100 kHz to 1 MHz. The MIS Schottky diode having interfacial insulator layer thickness of 33 Å, calculated from the measurement of the insulator capacitance in the strong accumulation region. At each frequency, the measured capacitance decreases with increasing frequency due to a continuous distribution of the interface states. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_b) values of 1.766 and 0.786 eV, respectively, were obtained from a forward bias I-V plot. In addition, the interface states distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) for the Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer, the interface states and barrier inhomogeneity of the device. As expected, the C-V curves gave a barrier height value higher than those obtained from I-V measurements. This discrepancy is due to the different nature of the I-V and C-V measurement techniques.     

Electrical analysis of organic dye-based MIS Schottky contacts

In this work, we prepared metal/interlayer/semiconductor (MIS) diodes by coating of an organic film on p-Si substrate. Metal(Al)/interlayer(Orange GOG)/semiconductor(p-Si) MIS structure had a good rectifying behavior. By using the forward-bias I-V characteristics, the values of ideality factor (n) and barrier height (BH) for the Al/OG/p-Si MIS diode were obtained as 1.73 and 0.77 eV, respectively. It was seen that the BH value of 0.77 eV calculated for the Al/OG/p-Si MIS diode was significantly larger than the value of 0.50 eV of conventional Al/p-Si Schottky diodes. Modification of the potential barrier of Al/p-Si diode was achieved by using thin interlayer of the OG organic material. This was attributed to the fact that the OG organic interlayer increased the effective barrier height by influencing the space charge region of Si. The interface-state density of the MIS diode was found to vary from 2.79 × 10¹³ to 5.80 × 10¹² eV⁻¹ cm⁻².     

Extraction of electronic parameters of Schottky diode based on an organic Orcein

An Au/Orcein/p-Si/Al device was fabricated and the current-voltage measurements of the devices showed diode characteristics. Then the current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) characteristics of the device were investigated at room temperature. Some junction parameters of the device such as ideality factor, barrier height, and series resistance were determined from I-V and C-V characteristics. The ideality factor of 2.48 and barrier height of 0.70 eV were calculated using I-V characteristics. It has been seen that the Orcein layer increases the effective barrier height of the structure since this layer creates the physical barrier between the Au and the p-Si. The interface state density N_ss were determined from the I-V plots. The capacitance measurements were determined as a function of voltage and frequency. It was seen that the values of capacitance have modified with bias and frequency.     

Electrical parameters of a DC sputtered Mo/n-type 6H-SiC Schottky barrier diode

A Mo/n-type 6H-SiC/Ni Schottky barrier diode (SBD) was fabricated by sputtering Mo metal on n-type 6H-SiC semiconductor. Before the formation of Mo/n-type 6H-SiC SBD, an ohmic contact was formed by thermal evaporation of Ni on n-type 6H-SiC and annealing at 950 °C for 10 min. It was seen that the structure had excellent rectification. The electrical parameters were extracted using its current–voltage (I–V) and capacitance–voltage (C–V) measurements carried out at room temperature. Very high (1.10 eV) barrier height and 1.635 ideality factor values were reported for Mo/n-type 6H-SiC using ln I–V plot. The barrier height and series resistance values of the diode were also calculated as 1.413 eV and 69 Ω from Norde׳s functions, respectively. Furthermore, 1.938 eV barrier height value of Mo/n-type 6H-SiC SBD calculated from C–V measurements was larger than the one obtained from I–V data.     

The analysis of I-V characteristics of Schottky diodes by thermionic emission with a Gaussian distribution of barrier height

The current-voltage (I-V) characteristics of Al/p-Si Schottky barrier diode (SBD) with native insulator layer were measured in the temperature range of 178-440 K. The estimated zero-bias barrier height Φ_B0 and the ideality factor n assuming thermionic emission (TE) theory have shown strong temperature dependence. Evaluation of the forward I-V data have revealed an increase of zero-bias barrier height Φ_B0 but the decrease of ideality factor n with the increase in temperature. The experimental and theoretical results of the tunneling current parameter E_o against kT/q were plotted to determine predominant current-transport mechanism. But the experimental results were found to be disagreement with the theoretical results of the pure TE, the thermionic-field emission (TFE) and the field emission (FE) theories. The conventional Richardson plot has exhibited non-linearity below 240 K with the linear portion corresponding to the activation energy of 0.085 eV and Richardson constant (A^*) value of 2.48 × 10⁻⁹ A cm⁻² K⁻² which is much lower than the known value of 32 A cm⁻² K⁻² for holes in p-type Si. Such behaviours were attributed to Schottky barrier inhomogeneities by assuming a Gaussian distribution of barrier heights (BHs) due to barrier height inhomogeneities that prevail at interface. Thus, the modified ln(I_o/T²) − q2σo2/2k²T² vs q/kT has plotted. Then A^* was calculated as 38.79 A cm⁻² K⁻² without using the temperature coefficient of the barrier height. This value of the Richardson constant 38.79 A cm⁻² K⁻² is very close to the theoretical value of 32 A K⁻² cm⁻² for p-type Si. Hence, it has been concluded that the temperature dependence of the forward I-V characteristics of the Al/p-Si Schottky barrier diodes with native insulator layer can be successfully explained on the basis of TE mechanism with a Gaussian distribution of the barrier heights.     

Thermally annealed Ni/n-GaAs(Si)/In Schottky barrier diodes

We have identically prepared as many as eight Ni/n-GaAs/In Schottky barrier diodes (SBDs) using an n-type GaAs substrate with a doping density of about 7.3 × 10¹⁵ cm⁻³. The thermal stability of the Ni/n-GaAs/In Schottky diodes has been investigated by means of current-voltage (I-V) techniques after annealed for 1 min in N₂ atmosphere from 200 to 700 °C. For Ni/n-GaAs/In SBDs, the Schottky barrier height Φ_b and ideality factor n values range from 0.853 ± 0.012 eV and 1.061 ± 0.007 (for as-deposited sample) to 0.785 ± 0.002 eV and 1.209 ± 0.005 (for 600 °C annealing). The ideality factor values remained about unchanged up to 400 °C annealing. The I-V characteristics of the devices deteriorated at 700 °C annealing.     

Temperature dependent current-voltage characteristics of the Zn/ZnO/n-Si/Au-Sb structure with ZnO interface layer grown on n-Si substrate by SILAR method

This is the first time; it was employed Successive Ionic Layer Adsorption and Reaction (SILAR) method in order to prepare Zn/ZnO/n-Si/Au-Sb sandwich structure. The ZnO interface layer was directly formed on n-type Si substrate using SILAR method. The X-ray diffraction (XRD) and scanning electron microscopy (SEM) studies were showed that the film is covered well on n-type Si substrate and have polycrystalline structure. An Au-Sb electrode was used as an ohmic contact. The Zn/ZnO/n-Si/Au-Sb sandwich structure demonstrated clearly rectifying behavior by the current-voltage (I-V) curves studied at room temperature. The sample temperature effect on the current-voltage (I-V) characteristics of Zn/ZnO/n-Si/Au-Sb structure was investigated in temperature range 80-320 K by steps of 20 K. The parameters such as barrier height, ideality factor and series resistance of this structure were calculated from the forward bias I-V characteristics as a function of sample temperature. It was seen that the ideality factor and series resistance were decreased; the barrier height were increased with increasing temperature. The experimental values of barrier height and ideality factor for this device were calculated as 0.808 eV and 1.519 at 320 K; 0.220 eV and 4.961 at 80 K, respectively. These abnormal behaviors can be explained by the barrier inhomogeneities at the metal-semiconductor (M-S) interface.     

The role of the interface insulator layer and interface states on the current-transport mechanism of Schottky diodes in wide temperature range

In order to interpret in detail the experimentally observed current-voltage-temperature (I-V-T) and capacitance-voltage-temperature (C-V-T) results of Al/p-Si metal-semiconductor Schottky barrier diodes (SBDs) we have been examined the samples in the temperature range of 150-375 K. In the calculation method, to confirm the relationship between the I-V-T and C-V-T results, we have reported a modification which includes the ideality factor, n, and tunnelling parameter δχ^1/2 in the forward bias current characteristics. In the intermediate bias voltage region (0.1 < V < 0.6 V), the semi-logarithmic plots of the forward I-V-T curves were found to be linear. From the reverse saturation currents I₀ obtained by extrapolating the linear region of curves to zero applied voltage, the values of zero bias barrier heights ?_B0 were calculated at each temperature. The values of ideality factor calculated from the slope of each curves were plotted as a function of temperature. The values of n are 3.41-1.40 indicating that the Al/p-Si diode does obey the thermionic field emission (TFE) mechanism rather than the other transport mechanism, particularly at low temperature. The high value of ideality factors is attributed to high density of interface states in the SBDs. The temperature dependence energy density distribution profile of interface state was obtained from the forward bias I-V-T measurements by taking into account the bias dependence of the effective barrier height and ideality factor. The interface states density N_ss decreasing with increasing temperature was interpreted by the result of atomic restructuring and reordering at the metal-semiconductor interface. After the modification was made to the forward current expression, we obtained a good agreement between the values of barrier height obtained from both methods over a wide temperature.     

The interface states analysis of the MIS structure as a function of frequency

The energy distribution of interface states (N_ss) and their relaxation time (τ) were of the fabricated the Al/SiO₂/p-Si (MIS) structures were calculated using the forward bias current-voltage (I-V), capacitance-frequency (C-f) and conductance-frequency (G-f) measurements. Typical ln[I/(1 − exp(−qV/kT)] versus V characteristics of MIS structure under forward bias show one linear region. From this region, the slope and the intercept of this plot on the current axis allow to determine the ideality factor (n), the barrier height (Φ_b) and the saturation current (I_S) evaluated to 1.32, 0.77 eV and 3.05 × 10⁻⁹ A, respectively. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer at metal-semiconductor interface, the interface states and barrier inhomogeneity of the device. The energy distribution of interface states (N_ss) and their relaxation time (τ) have been determined in the energy range from (0.37 − E_v) to (0.57 − E_v) eV. It has been seen that the N_ss has almost an exponential rise with bias from the mid gap toward the top of valance band. In contrary to the N_ss, the relaxation time (τ) shows a slow exponential rise with bias from the top of the E_v towards the mid gap energy of semiconductor. The values of N_ss and τ change from 6.91 × 10¹³ to 9.92 × 10¹³ eV⁻¹ cm⁻² and 6.31 × 10⁻⁴ to 0.63 × 10⁻⁴ s, respectively.     

Electrical and photovoltaic properties of a n-Si/chitosan/Ag photodiode

The electrical and photovoltaic properties of AuSb/n-Si/chitosan/Ag diode have been investigated. The ideality factor, barrier height and Richardson constant values of the diode at room temperature were found to be 1.91, 0.88 eV and 121.4 A/cm² K², respectively. The ideality factor of the diode is higher than unity, suggesting that the diode shows a non-ideal behaviour due to series resistance and barrier height inhomogeneities. The barrier height and ideality factor values of Ag/CHT/n-Si diode at room temperature are significantly larger than that of the conventional Ag/n-Si Schottky diode. The φ_B value obtained from C-V measurement is higher than that of φ_B value obtained from I-V measurement. The discrepancy between φ_B(C-V) and φ_B(I-V) barrier height values can be explained by Schottky barrier height inhomogeneities. AuSb/n-Si/chitosan/Ag diode indicates a photovoltaic behaviour with open circuit voltage (V_oc = 0.23 V) and short-circuit current density (J_sc = 0.10 μA/cm⁻²) values.     

Analysis of electronic parameters and interface states of boron dispersed triethanolamine/p-Si structure by AFM, I-V, C-V-f and G/ω-V-f techniques

The electronic parameters and interface state properties of boron dispersed triethanolamine/p-Si structure have been investigated by atomic force microscopy, I-V, C-V-f and G/ω-V-f techniques. The surface topography and phase image of the TEA-B film deposited onto p-Si substrate were analyzed by atomic force microscopy. The atomic force microscopy results show a homogenous distribution of boron particles in triethanolamine film. The electronic parameters (barrier height, ideality factor and average series resistance) obtained from I-V characteristics of the diode are 0.81 eV, 2.07 and 5.04 kΩ, respectively. The interface state density of the diode was found to be 2.54 × 10¹⁰ eV⁻ cm⁻² under V_g = 0. The obtained D_it values obtained from C-V and G/ω measurements are in agreement with each other. The profile of series resistance dependent on voltage and frequency confirms the presence of interface states in boron dispersed triethanolamine/p-Si structure. It is evaluated that the boron dispersed triethanolamine controls the electronic parameters and interface properties of conventional Al/p-Si diode.