Four-layer resist process for asymmetric gate recess

In this paper, we present an optimized four-layer resist (PMMA and its copolymers) process for the fabrication of T-shaped gates used in compound semiconductor field effect transistors (FETs). The process is capable of producing a profile which acts as both the etch mask for the wide, asymmetric recess trench as well as the liftoff mask for a T-shaped gate metal. The resist profile is achieved in a single step using electron beam lithography, eliminating the need for two separate lithography steps and the crucial alignment between them. Gate lengths of 100 nm are achieved using this process. Recess widths on the drain side of the gate range from 50 to 300 nm, and recess widths on the source side of the gate are 50 nm.     

Submicron T-shaped gate HEMT fabrication using deep-UV lithography

A new combination of low/high/low sensitivity tri-layer (PMMA/PMIPK/PMMA) resist system was used for deep UV lithography to-fabricate submicron T-shaped gate. Gate length as narrow as 0.2 μm is achieved. GaAs HEMTs with 0.3 μm T-shaped Ti/Pt/Au gate are fabricated using this technology. The HEMT demonstrated a 0.6 dB noise figure and 13 dB associated gain at 10 GHz. This deep UV lithography process provides a high throughput and low cost alternative to E-beam lithography for submicron T-gate fabrication     

Electron-beam fabrication of GaAs low-noise MESFET's using a new trilayer resist technique

A LO/HI/LO resist system has been developed to produce sub-half-micrometer T-shaped cross section metal lines using e-beam lithography. The system provides T-shaped resist cavities with undercut profiles. T-shaped metal lines as narrow as 0.15 µm have been produced. GaAs MESFET's with 0.25-µm T-shaped Ti/Pt/Au gates have also been fabricated on MBE wafers using this resist technique. Measured end-to, end 0.25-µm gate resistance was 80 ω/mm, dc transconductance gmas high as 300 mS/mm was observed. At 18 GHz, a noise figure as low as 1.4 dB with an associated gain of 7.9 dB has also been measured. This is the lowest noise figure ever reported for conventional GaAs MESFET's at this frequency. These superior results are mainly attributed to the high-quality MBE material and the advanced T-gate fabrication technique employing e-beam lithography.     

0.15 μm T-shaped gate fabrication for GaAs MODFET using phaseshift lithography

A new fabrication process of GaAs MODFETs with 0.15 micron T-shaped gate has been developed by using phase shift lithography. Sub-quarter micron footprints of T-shaped gates are defined as line patterns by PEL (pattern-edge line) method using chemically stable positive photoresist. Parasitic capacitances such as C_gs and C_gd are also reduced by the air-gap incorporated in the present process. An implemented GaAs MODFET exhibited the NF of 0.36 dB and the gain of 11.5 dB at the frequency of 12 GHz     

0.1μm T型栅PHEMT器件

通过电子束和接触式曝光相结合的混合曝光方法,并利用复合胶结构,一次电子束曝光制作出具有T型栅的PHEMT器件,并对0.1μm栅长PHEMT器件的整套工艺及器件性能进行了研究．形成了一整套具有新特点的PHEMT器件制作工艺,获得了良好的器件性能(ft=93.97GHz;gm=690mS/mm)．     

同步辐射x射线光刻制作深亚微米T形栅

x射线光刻非常适合用于深亚微米T形栅的制作,这是因为它的高分辨率、大的曝光视场和高的生产效率足以满足MMIC制造工艺的要求。本文中我们首先对我们的x射线掩模制造工艺进行介绍,然后论述了一种用于制造深亚微米T形栅的两层胶工艺,介绍了所取得的一些研究结果,最后对国内的深亚微米光刻现状进行了简要分析。     

0.2 Micron length T-shaped gate fabrication using angle evaporation

A new technique has been developed to generate sub-half-micron T-shaped gates in GaAs MESFET's. The technique uses a single-level resist and an angle evaporation process. By using this technique, T-shaped gates with lengths as short as 0.2 µm near the Schottky interface have been fabricated. Measured gate resistance from this structure was 6.1 Ω/mm gate width which is the lowest value ever reported for gates of equal length. GaAs single- and dual-gate MESFET's with 0.3 µm long T-shaped gates have also been fabricated. At 18 GHz, maximum available gain of 9.5 dB in the single-gate FET and maximum stable gain of 19.5 dB in the dual-gate device have been measured.     

Lithography scaling issues associated with III–V MOSFETs

In this work we investigate fabrication issues associated with scaling down the gate length and source drain contact separation of a III–V MOSFET. We used high resolution electron-beam lithography and lift-off for gate and ohmic contact patterning to fabricate gate-last lithographically-aligned MOSFETs. This work considers the effect of variations in resist thickness on gate lengths and also the fabrication of long narrow gaps using electron-beam lithography. The study showed that the effect of resist thickness variation on metal linewidth is insignificant. A difference of around 2–3 nm was found between PtAu linewidths fabricated using 150 and 280 nm thick resist. A VB6 lithography tool was found to be useful for linewidth measurements. We showed that the choice of resist is critical to gap formation, and that PMMA is not well suited to this task.     

Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication

As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. In recent CMOS technologies, side-wall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present approach to overcome these fabrication limitations. The spacer patterning technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical integrated lithography and etching processes. Generally relates to semiconductor manufacturing, and more particularly to nanotechnology fabrication feasibility for CMOS wafer process on gate spacer technology manufacture feasibility. A modified side-wall spacer patterning method was implemented for using conventional lithography and etching processing technology. Based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure, a novel integrated process for well controlled side-wall spacer formation was developed for fabrication.     

A simple method for sub-100 nm pattern generation with I-line double-patterning technique

We have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100 nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal-oxide-semiconductor field-effect transistors. Excellent device characteristics were verified.     

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured     

200nm栅长In0.52Al0.48As／In0.6Ga0.4As MHEMTs器件

利用电子束光刻技术制备出200nm栅长GaAs基InAIAs/InGaAs MHEMT器件.Ti/Pt/Au蒸发作为栅极金属.同时为了减少栅寄生电容和寄生电阻,采用3层胶工艺,实现了T 型栅. GaAs基MHEMT 器件获得了优越的直流和高频性能,跨导、饱和漏电流密度、域值电压、电流增益截止频率和最大振荡频率分别达到510mS/mm, 605mA/mm, -1.8V, 110GHz及 72GHz,为进一步研究高性能GaAs基MHEMT器件奠定了基础.     

A quadruple well, quadruple polysilicon BiCMOS process for fast 16Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm² with conventional I-line lithography and 7.32 μm² with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance     

200nm栅长In0.52Al0.48As/In0.6Ga0.4As MHEMTs器件

利用电子束光刻技术制备出200nm栅长GaAs基InAlAs/InGaAs MHEMT器件.Ti/Pt/Au蒸发作为栅极金属.同时为了减少栅寄生电容和寄生电阻,采用3层胶工艺,实现了T型栅.GaAs基MHEMT 器件获得了优越的直流和高频性能,跨导、饱和漏电流密度、域值电压、电流增益截止频率和最大振荡频率分别达到510mS/mm,605mA/mm,-1.8V,110GHz及72GHz,为进一步研究高性能GaAs基MHEMT器件奠定了基础.     

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.     

A high aspect-ratio 0.1 micron gate technique for low-noise MESFET'S

A new technique, using optical lithography, has been developed to produce very thick submicron gates. This technique has produced Al gates 900Å long and 1.7µm thick, for an aspect-ratio (gate thickness/gate length) of ∼ 19. Using this high aspect-ratio gate structure, GaAs MESFET's have been fabricated with gate lengths as short as 0.1µm and widths as wide as 300µm. Gate resistances of 17Ω/mm and 37Ω/mm of gate width have been measured for half-micron and quarter-micron long Al gates, respectively.     

A gallium arsenide overlapping-gate charge-coupled device

We have developed a new CCD fabrication process for producing an overlapping gate structure which permits submicrometer control of the gap size while using conventional lithography. This process has been used to fabricate four-phase 16-stage Schottky barrier CCD's on GaAs with charge transfer inefficiencies of less than 2 × 10^-4at a 1-MHz clock rate, indicating that charge loss due to potential troughs between the gates has been essentially eliminated. This control of the gap permits the CCD channel to be of submicrometer thickness, which simplifies the integration of CCD's with high-speed devices requiring submicrometer channel thicknesses.     

0.5μm AlGaN/GaN HEMT及其应用

报道了采用I线步进光刻实现的76.2 mm SiC衬底0.5μm GaN HEMT.器件正面工艺光刻均采用了I线步进光刻来实现,背面用通孔接地.栅脚介质刻蚀采用一种优化的低损伤RIE刻蚀方法实现了60°左右的侧壁倾斜角,降低了栅脚附近峰值电场强度,提高器件性能和可靠性.研制的GaN HEMT器件fT为15 GHz,fm...     

基于X光移动光刻技术的PMMA微透镜阵列制备

微透镜阵列的制备已经成为微光学领域的研究热点。利用两次X光移动光刻技术,以聚甲基丙烯酸甲酯(PMMA)为正光刻胶,在PMMA基板上制造了微透镜阵列,并对其制作原理进行了详细说明。设计了制备微透镜阵列用的掩膜图形,并通过掩膜图形模拟仿真,预测了微透镜在两次移动曝光显影后的形状。第一次X光移动光刻后,理论上会得到半圆柱状三维结构;第一次光刻后将掩膜板旋转90,进行第二次移动曝光光刻,最终在PMMA基板上制备了面积为10 mm10 mm的3030个微透镜阵列,阵列中每个微透镜的直径约248m、厚度约82m。同时也研究了X光曝光量与PMMA刻蚀深度之间的关系。微透镜阵列形貌测试表明此种制备微透镜阵列的新方法是可行的。     

Electrical properties of sub-100 nm SiGe nanowires

In this study, the electrical properties of SiGe nanowires in terms of process and fabrication integrity, measurement reliability, width scaling, and doping levels were investigated. Nanowires were fabricated on SiGe-on oxide (SGOI) wafers with thickness of 52 nm and Ge content of 47%. The first group of SiGe wires was initially formed by using conventional I-line lithography and then their size was longitudinally reduced by cutting with a focused ion beam (FIB) to any desired nanometer range down to 60 nm. The other nanowire group was manufactured directly to a chosen nanometer level by using sidewall transfer lithography (STL). It has been shown that the FIB fabrication process allows manipulation of the line width and doping level of nanowires using Ga atoms. The resistance of wires thinned by FIB was 10 times lower than STL wires which shows the possible dependency of electrical behavior on fabrication method.