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分析了电荷泵型锁相环中鉴相器和电荷泵的非理想因素及优化设计方法。基于台积电公司(TSMC)0.35μm 2层多晶硅4层金属(2P4M)CMOS工艺,设计了一种低杂散的鉴频鉴相器结构,该结构通过"自举"的方法,用单位增益放大器使充放电前后开关管各节点处的电压保持不变,从而消除了电荷共享的影响,减小了鉴相器的输出杂散。仿真结果表明相比于传统鉴相器结构,该鉴频鉴相器有效抑制了电荷共享问题,电荷泵开关管开启时的充放电电流尖峰大大减小了,鉴相前后的电压波动小于200μV,脉冲尖峰仅为3.07 mV,有效降低了鉴频鉴相器的输出杂散。 相似文献
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采用高匹配电荷泵电路和高精度自动频率校准(AFC)电路,设计了一种低功耗低参考杂散电荷泵锁相环。锁相环包括D触发鉴频鉴相器、5 bit数字可编程调频LC压控振荡器(VCO)、16~400可编程分频器和AFC模块。采用高匹配电荷泵,通过增大电流镜输出阻抗的方法,减少电荷泵充放电失配。同时,AFC电路采用频段预选快速搜索方法,实现了低压控增益LC VCO精确频带锁定,扩展了振荡频率范围,且保持了较低的锁相环输出参考杂散。锁相环基于40 nm CMOS工艺设计,电源电压为1.1 V。仿真结果表明,电压匹配范围为0.19~0.88 V,振荡频率范围为5.9~6.4 GHz,功率小于6.5 mW@6 GHz,最大电流失配小于0.2%@75μA;当输出信号频率为6 GHz时,输出相位噪声为-113.3 dBc/Hz@1 MHz,参考杂散为-62.3 dBc。 相似文献
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本文提出了一种新型高速低抖动锁相环架构。通过实时监测鉴频鉴相器的输出产生线性斜坡电荷泵电流,实现了自适应带宽控制。主要通过在传统锁相环的基础上,巧妙地设计了一个快速启动电路和一个斜坡电荷泵电路。首先,使能快速启动电路实现对环路滤波器的快速预充电;然后当鉴频鉴相器输出的充电电流脉宽超过设定的最小值时,斜坡电流控制电路将线性增加电荷泵电流,从而实现了快速响应和低相位噪声。同时,通过零温度系数电荷泵电流的设计,保证了高速低抖动指标的温度稳定性。所设计的新型锁相环架构已在一款基于0.35 μm的DSP处理芯片中得到验证。测试结果显示所设计斜坡电荷泵锁相环在宽温度范围内使得锁定时间提高了60%,且峰峰值抖动仅有0.3%的良好特性。 相似文献
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用SMIC0.18μmCMOS工艺设计了一种改进型电荷泵电路。该电路基本思想是使用电流参考支路和运放来实现充放电电流的高度匹配,改进则基于重复利用运放的考虑。传统结构为了消除电荷共享效应需要一个单位增益运放,而这一设计省去这个运放,简化了设计,同时也能够达到充放电电流的良好匹配。芯片测试结果显示,输出电压在0.4~1.4V的范围内,电荷泵充放电电流约为1.1mA,失配小于2%。 相似文献
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采用动态鉴频鉴相器、基于常数跨导轨到轨运算放大器的电荷泵、差分型环形压控振荡器,设计了一种低抖动的电荷泵锁相环。基于SMIC 0.18-μm CMOS工艺,利用Cadence软件完成了电路的设计与仿真。结果表明,动态的鉴频鉴相器,有效消除了死区。新型的电荷泵结构,在输出电压为0.5 V~1.5 V时将电流失配减小到了2%以下。压控振荡器在频率为1 MHz时输出的相位噪声为-94.87 dB在1 MHz,调谐范围为0.8 GHz~1.8 GHz。锁相环锁定后输出电压波动为2.45 mV,输出时钟的峰峰值抖动为12.5 ps。 相似文献
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采用TSMC 0.18 μm 混合CMOS工艺,设计了一种应用在1.571 GHz GNSS接收机中低杂散锁相环的鉴频鉴相器与电荷泵电路。鉴频鉴相器采用两相非重叠时钟结构和延时可控电路,实现了鉴频鉴相器的延时失配最小化和导通时间可调,在降低杂散的同时消除死区。电荷泵采用4路控制信号和1路可控充电和放电电路,有效地优化了电流失配和电荷泵电流的大小,进一步降低锁相环的杂散。测试结果表明,在电源电压为1.8 V,电荷泵电流为100 μA 时,延时失配和充放电电流失配近似为0,杂散为-71.77 dBc@16.375 MHz。 相似文献
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Karaca H. Kilinc S. Yuksel Y. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2005,52(6):304-307
Resonant inverters mostly employ tuning loops based on a phase-locked-loop (PLL) circuit. Some commercially available PLL chips, frequently used in this application, include a voltage output charge-pump phase frequency detector (CP/PFD) rather than well-known current output CP/PFD, which complicates the analysis of the loop. We present a new model for voltage output CP/PFD and an analysis of a tuning loop using this model. The proposed model employs the resistance multiplication approach, which is applicable for the circuits containing periodically operated switches. It is shown that a voltage output CP/PFD in conjunction with a simple RC low-pass filter can be modeled using a dc voltage source, a phase error controlled resistor, and a capacitor. The theoretical study is verified by experimental results. 相似文献
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Xiang Jiang Xuecheng Zou Dingzhong Xiao Sanqing Liu 《Circuits, Systems, and Signal Processing》2006,25(1):111-124
A self-balanced charge pump (CP) to achieve nearly zero phase
error is proposed and analyzed. The proposed topology is based
on an additional mirror CP and mirror phase/frequency detector
(PFD). The mirror CP and PFD balance charges and generate a
bias for the master CP. The proposed CP is designed based on
the SMIC 0.25-μm 1P5M CMOS process with a 2.5-V supply
voltage. HSPICE simulation shows that even if the mismatch of
the PFD were beyond 10%, the charge pump could still keep
nearly zero phase error. The proposed CP needs only one side of
bias current; the other side of the bias is self-balanced, so it
is irrelevant to the current mismatch. 相似文献
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一种适用于NRZ数据的时钟数据恢复电路 总被引:1,自引:0,他引:1
提出了一种基于传统电荷泵锁相环结构的时钟数据恢复电路.采用一种适用于NRZ数据的新型鉴频鉴相器电路,以克服传统鉴频鉴相器在恢复NRZ信号时出现错误脉冲的问题,从而准确地恢复出NRZ数据.同时,对其他电路也采用优化的结构,以提高时钟数据恢复电路的性能.设计的电路可在1.1 V超低电压下工作,适合RF ID等需要低电压、低功耗的系统使用. 相似文献
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Soh Lip-Kai Mohd-Shahiman Sulaiman Zubaida Yusoff 《Analog Integrated Circuits and Signal Processing》2008,55(2):149-154
In this paper, a dual charge pump architecture for fast-lock delay-locked loop (DLL) is proposed and analyzed. The proposed
fast lock DLL uses only one phase frequency detector (PFD) to perform dual path tuning and a lock control circuit to control
the switching between the two path. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse
produced when the reference signal and feedback signal is in phase. The proposed DLL circuit is designed based on the Silterra
0.18-μm 1P6M CMOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 × 116.16 μm.
An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking properties. 相似文献
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Arora H. Klemmer N. Morizio J.C. Wolf P.D. 《IEEE transactions on circuits and systems. I, Regular papers》2005,52(2):379-395
Mathematical models for the behavior of fractional-N phase-locked-loop frequency synthesizers (Frac-N) are presented. The models are intended for calculating rms phase error and determining spurs in the output of Frac-N. The models describe noise contributions due to the charge pump (CP), the phase frequency detector (PFD), the loop filter, the voltage control oscillator, and the delta-sigma modulator. Models are presented for the effects of static CP gain mismatch, CP dynamic mismatch and PFD reset delay mismatch. A simple analytic expression shows the level of /spl Delta//spl Sigma/ sequence noise caused by static CP current mismatch. We further show that un-equal rise time and fall time constants of the CP result in dynamic mismatch noise. Reset delay mismatch in PFD is shown to also contribute significantly to close-in phase noise. The model takes into account the reduction in CP thermal and flicker noise due to the changing duty cycle of Frac-N CP. Our model is therefore useful in characterizing the noise performance of Frac-N at the system-level, simplifying the design of fractional-N synthesizers and transmitters. Analytical and simulated results are compared and show good agreement with prior published data on Frac-N realizations. 相似文献
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To extend the linearity range of the phase-frequency detector/charge pump
(PFD/CP) circuit, a modular design for a novel PFD architecture is proposed. The new
circuit yields a modular extension range of –2N to 2N, where N is an integer
representing the order of the PFD/CP extension. The efficacy of the new PFD/CP is
demonstrated by the improved frequency acquisition time obtained via closed-loop
simulation. Hence, the developed architecture is a good candidate for phase-locked loops
requiring the use of PFD/CP with a broad linear range of operation. 相似文献
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A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende... 相似文献
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A new phase self-calibrated scheme maintains the quadrature is proposed in the letter, which mainly includes quadrature phase
detector (QPD), charge pump, comparator, controller and variable delay buffer (VDB) etc. The primary idea behind the scheme
is that the quadrature phase error is converted to the voltage variation on the capacitor, and then the voltage variation
drives the controller to tune the VDB to the proper control word. The phase calibration is digitally controlled and considers
the mismatch effect of charge pump, removing the disadvantage of conventional analog calibration circuit whose performance
is sensitive to process and temperature variations and aging. It is shown that the two VDBs have an 8°quadrature phase shift
tuning range, and an 8 mA current at 1.7 HGz, and the calibration process takes less than 160 μs. 相似文献
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Bo Zhao Xiaojian Mao Huazhong Yang Hui Wang 《Analog Integrated Circuits and Signal Processing》2009,59(3):265-273
A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator
(VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8
prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator
(SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is
proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype
circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise
is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias.
Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz. 相似文献
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《Microelectronics Journal》2014,45(6):740-750
A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm2. 相似文献