Radiation damage of thermally oxidized MOS capacitors

The influence of preparation parameters and the effect of X-rays (150 keV, 10⁴rad (Si)) on oxide charge Qoxand interface state density Nssin thermally oxidized MOS varactors under different biasing conditions during irradiation has been investigated. The interface state density was determined by the ac conductance method before and after irradiation. The oxide charge has been evaluated with regard to the charge Qssof the interface states. Qsshas beeu discussed with the aid of simple models concerning the energetic distribution and recharge character of the interface states. The results indicate a similar dependence between flatband voltage, interface state density, and normalized oxide charge density as a function of gate bias during irradiation. Furthermore, the so-called "oxidation triangle" of oxide charge before irradiation exists for interface states as well. Calculations on the basis of the Schottky barrier model of the irradiated MOS structure show that the radiation-induced charge exists at both interfaces in the oxide layer. Radiation tolerance of the MOS capacitors as a function of technological parameters is discussed.     

Threshold and sheet concentration sensitivity of high electron mobility transistors

We present results of an analysis of the dependence of the threshold voltage and the sheet carrier concentration on background substrate doping, Al1 - xGaxAs doping, thickness, and metal barrier height in the high electron mobility transistor (HEMT) at room and liquid nitrogen temperatures. The sensitivity of threshold voltage and sheet carrier concentration to buffer layer or substrate background concentrations improves at lower temperatures. The sensitivity of threshold voltage and sheet carrier concentration to Ga1 - xAlxAs doping and thickness degrades at lower temperatures. The threshold sensitivity to barrier height is temperature independent but increases for sheet carrier concentration at lower temperatures. The design of a device structure for integrated circuit application with minimial threshold variations will require an optimal design of the device and will depend on the status of control of the various parameters.     

Modeling on oxide dependent 2DEG sheet charge density and threshold voltage in AlGaN/GaN MOSHEMT

We have developed a physics based analytical model for the calculation of threshold voltage, two dimensional electron gas (2DEG) density and surface potential for AlGaN/GaN metal oxide semiconductor high electron mobility transistors (MOSHEMT). The developed model includes important parameters like polarization charge density at oxide/AlGaN and AlGaN/GaN interfaces, interfacial defect oxide charges and donor charges at the surface of the AlGaN barrier. The effects of two different gate oxides (Al₂O₃ and HfO₂) are compared for the performance evaluation of the proposed MOSHEMT. The MOSHEMTs with Al₂O₃ dielectric have an advantage of significant increase in 2DEG up to 1.2×10¹³ cm^-2 with an increase in oxide thickness up to 10 nm as compared to HfO₂ dielectric MOSHEMT. The surface potential for HfO₂ based device decreases from 2 to -1.6 eV within 10 nm of oxide thickness whereas for the Al₂O₃ based device a sharp transition of surface potential occurs from 2.8 to -8.3 eV. The variation in oxide thickness and gate metal work function of the proposed MOSHEMT shifts the threshold voltage from negative to positive realizing the enhanced mode operation. Further to validate the model, the device is simulated in Silvaco Technology Computer Aided Design (TCAD) showing good agreement with the proposed model results. The accuracy of the developed calculations of the proposed model can be used to develop a complete physics based 2DEG sheet charge density and threshold voltage model for GaN MOSHEMT devices for performance analysis.     

Switching times variation of power MOSFET devices after electrical stress

The switching performance of three power MOSFET devices with different oxide thicknesses is studied after several periods of electrical stress. The thickest oxide reveals a large accumulation of positive charges in the oxide bulk after small periods of stress. These charges affect the switching parameters by increasing the rise time and by decreasing the fall time. Larger periods of stress reduce the effect of positive charges by increasing the number of interface states. The threshold voltage is decreased by the effect of a positive oxide charge and increases with the appearance of interface states. All these phenomena are less observable as we reduce the oxide thickness.     

基于电荷泵技术的MOS器件界面特性测量方法

随着CMOS工艺的发展,栅介质层厚度不断减薄,导致栅漏电流不断增大,这使传统测量界面态的方法应用受到限制。介绍了采用电荷泵技术用于MOS器件Si/SiO2界面特性研究,分别研究了脉冲频率、反偏置电压、脉冲幅值和占空比对泵电流的影响,对突变曲线做了深入的理论分析,指出了需要严格的选择脉冲频率、幅值、反偏置电压和占空比,才能保证测量的准确性。这些探索为电荷泵技术在MOS器件中的界面电荷测量和电荷泵曲线分析提供实验指导和理论依据。     

非晶IGZO薄膜晶体管开启区电流的解析模型

对非晶In-Ga-Zn-Oxide薄膜晶体管,假设能隙中陷阱态密度呈指数分布,给出了解析的电流模型。运用薄层电荷近似的方法推导陷落电荷和自由电荷表达式,并基于此给出了基于表面势的电流表达式。在此电流表达式的基础上,通过泰勒展开,给出了基于阈值电压的电流表达式。基于表面势和基于阈值电压的电流表达式的计算结果与测量数据相比较,符合得很好。     

注氟加固PMOSFET的电离辐射响应与时间退火效应

研究了注F加固PMOSFET的总剂量辐照响应特性和辐照后由氧化物电荷、界面态变化引起的阈电压漂移与时间、温度、偏置等退火条件的关系，发现一定退火条件下注F加固PMOSFET由于界面态密度、特别是氧化物电荷密度继续增加，使得电路在电高辐照后继续损伤，探讨了加速MOS器件电离辐照感生界面态生长的方法。     

Polysilicon quantization effects on the electrical properties of MOS transistors

The quantum-mechanical behavior of charge carriers at the polysilicon/oxide interface is investigated. It is shown that a dark space depleted of free carriers is created at the interface as a consequence of the abrupt potential energy barrier, which dominates the polysilicon capacitance and voltage drop in all regions of operation of modern MOS devices. Quantum-mechanical effects in polysilicon lead to a reduction in the gate capacitance in the same way as substrate quantization, and to a negative voltage shift, which is opposed to the positive shift caused by carrier quantization in the channel. Effects on the extraction of device physical parameters such as oxide thickness and polysilicon doping are also addressed.     

Flicker (1/f) noise generated by a random walk of electrons in interfaces

Flicker noise can be generated by a random walk of mobile electrons in interfaces via interface states. It is proposed that these electrons interact with surface phonons to form polarons, which have very low mobilities. The flicker-noise model is a general one and may be used to explain flicker noise on MOSFET's, clean Si surfaces, metallic resistors, grain boundaries, amorphous layers, electron tubes, metal-insulator-metal junctions, diodes, and transistors. The dependence of the noise intensity is calculated as a function of device parameters such as interface state density, source-drain current, source-drain voltage, gate voltage, oxide layer thickness, grain size, temperature, size of the cathode, diode current, base current, and the surface recombination in the emitter-base area. Hooge's parameter is calculated quantitatively for several devices.     

Time dependence of p-MOSFET hot-carrier degradation measured andinterpreted consistently over ten orders of magnitude

Hot-carrier degradation is measured and analyzed over ten orders of magnitude in time for three buried-channel p-MOSFET types with different oxide thicknesses. The effects of oxide charge and interface states are separated by using the charge-pumping technique. Two dominating effects are sufficient to account for the degradation. For worst case degradation, negative oxide charge and interface states are generated by electrons near the drain. This charge is distributed homogeneously over the oxide thickness and it attracts an inversion layer that extends the drain and reduces the effective transistor length logarithmically in time. Simultaneously, this inversion layer prevents substantial degradation related to the interface states, since it masks their effects. A simple model for the logarithmic time dependence is presented. At more negative gate voltages, holes cause interface states that reduce the transconductance with a power-law time dependence, comparable to the worst case n-MOSFET degradation     

On interfacial charges in the oxide layer of mis-type Ag- and Au-n GaAs Schottky barriers

Fixed interfacial charges in MIS type n-GaAs Schottky barriers were investigated by measuring the flatband voltage as a function of the oxide layer thickness in the range of 2–20 nm. The linear relationship obtained allowed the determination of the sign, the location and the density of these charges. In contrast to Si, negative charges were found here. They were located at less than 2 nm from the interface. From the dependence of the charge density on the annealing temperature the conclusion was reached that excess As at the oxide semiconductor interface is at the origin of these charges. The observed changes in work function difference at the interface caused by the annealing support a recent Schottky barrier theory developed by Woodall and Freeouf.     

Mechanisms for hot-carrier-induced degradation inreoxidized-nitrided-oxide n-MOSFET's under combined AC/DC stressing

Hot-carrier-induced degradation behavior of reoxidized-nitrided-oxide (RNO) n-MOSFETs under combined AC/DC stressing was extensively studied and compared with conventional-oxide (OX) MOSFETs. A degradation mechanism is proposed in which trapped holes in stressed gate oxide are neutralized by an ensuing hot-electron injection, leaving lots of neutral electron traps in the gate oxide, with no significant generation of interface states. The degradation behavior of threshold voltage, subthreshold gate-voltage swing, and charge-pumping current during a series of AC/DC stressing supports this proposed mechanism. RNO device degradation during AC stressing arises mainly from the charge trapping in gate oxide rather than the generation of interface states due to the hardening of the Si-SiO₂ interface by nitridation/reoxidation steps     

Analytical drain current model for amorphous IGZO thin-film transistors in above-threshold regime

An analytical drain current model is presented for amorphous In-Ga-Zn-oxide thin-film transistors in the above-threshold regime,assuming an exponential trap states density within the bandgap.Using a charge sheet approximation,the trapped and free charge expressions are calculated,then the surface potential based drain current expression is developed.Moreover,threshold voltage based drain current expressions are presented using the Taylor expansion to the surface potential based drain current expression.The calculated results of the surface potential based and threshold voltage based drain current expressions are compared with experimental data and good agreements are achieved.     

Tailoring Electron‐Transfer Barriers for Zinc Oxide/C60 Fullerene Interfaces

The interfacial electronic structure between oxide thin films and organic semiconductors remains a key parameter for optimum functionality and performance of next‐generation organic/hybrid electronics. By tailoring defect concentrations in transparent conductive ZnO films, we demonstrate the importance of controlling the electron transfer barrier at the interface with organic acceptor molecules such as C₆₀. A combination of electron spectroscopy, density functional theory computations, and device characterization is used to determine band alignment and electron injection barriers. Extensive experimental and first principles calculations reveal the controllable formation of hybridized interface states and charge transfer between shallow donor defects in the oxide layer and the molecular adsorbate. Importantly, it is shown that removal of shallow donor intragap states causes a larger barrier for electron injection. Thus, hybrid interface states constitute an important gateway for nearly barrier‐free charge carrier injection. These findings open new avenues to understand and tailor interfaces between organic semiconductors and transparent oxides, of critical importance for novel optoelectronic devices and applications in energy‐conversion and sensor technologies.     

Electrical testing for process evaluations

MOS LSI process evaluation techniques based on electrical measurements are presented. Important processing parameters, such as gate length, gate oxide thickness, junction depth and channel doping which determine major device characteristics, e.g. threshold voltage and gain factor, are evaluated by electrical measurements, and compared with those measured by optical or in-process monitoring methods. Good agreement between these results indicates the effectiveness of this electrical evaluation technique. According to the analysis, threshold voltage variations across the wafer are primarily due to variations in gate oxide thickness, while anomalous threshold voltage reduction in the short channel region is attributed to MOSFET punch-through.     

An analytical model for self-limiting behavior of hot-carrierdegradation in 0.25 μm n-MOSFET's

Hot-carrier degradation of short-channel n-MOSFETs becomes saturated after reaching a certain threshold value. The physical mechanism for this self-limiting behavior is investigated. It is proposed that the hot-carrier-induced oxide trapped charge and interface states form a potential barrier that repels subsequent hot carriers from causing further damage and can lead to the saturation of device degradation. A physical model is developed on the basis of the analysis. The model is verified by experimental results and can be used for more accurate device reliability projection     

An accurate two-dimensional CAD-oriented model of retrograde doped MOSFETs for improved short channel performance

An analytical CAD-oriented model for short channel threshold voltage of retrograde doped MOSFETs is developed. The model is extended to evaluate the drain induced barrier lowering parameter (R) and gradient of threshold voltage. The dependence of short channel threshold voltage and R on thickness of lightly doped layer (d) has also been analyzed in detail. It is shown that a retrograde doping profile reduces short channel effects to a considerable extent. A technique is developed to optimize the device parameters for minimizing short channel effects. The results so obtained are in close proximity with published data.     

Capacitance-voltage characteristics of Semiconductor-Insulator-Semiconductor (SIS) structure

The ideal low- and high-frequency capacitance-voltage curves of a semiconductor(2)-insulator-semiconductor(1) (SIS) structure were first calculated with the insulator thickness, conductivity types and doping concentrations in semiconductor(1) and semiconductor(2) as parameters. The effects of fixed oxide charge and interface trap charge on the low and high frequency capacitance-voltage curves were also calculated. It was found that the fixed oxide sheet charge density with its centroid and the order estimation of the interface trap charge density with its effective type in addition to the insulator thickness, conductivity types and doping concentrations in semiconductor(1) and semiconductor(2) could be estimated from measured low and high frequency capacitance-voltage curves of an SIS structure.     

用于电路模拟的4H-SiC MOSFET高温沟道电子迁移率模型

提出了适用于电路模拟的4H-SiC n-MOSFET高温沟道电子迁移率模型.在新模型中,引入了横向有效电场和表面粗糙散射的温度依赖性,电子饱和漂移速度与横向有效电场和温度的关系,以及改进的界面陷阱电荷和固定氧化物电荷库仑散射模型等因素.采用与温度-阈值电压实验曲线拟合的方法,确定了界面态参数和固定氧化物电荷.基于新迁移率模型的模拟结果与实验吻合.