应用于无线传感网的低功耗PGA设计

可编程增益放大器(PGA)主要应用于无线传感网络射频前端接收机芯片.PGA的设计采用0.18 μm RF CMOS工艺,以负载可编程为基础实现增益可变.PGA电压增益范围1～60 dB,增益步长1 dB,增益误差小于0.5 dB,中心频率为2MHz,3 dB带宽大于3.2 MHz.通过控制放大器尾电流源工作与否来实现功耗管理.当电源电压为1.8 V时,最大功耗为4mw,最小功耗为1.3 mW.通过仿真验证,PGA性能能够满足系统设计要求.     

一个具有40dB增益、4.5dB噪声系数的应用于6-7GHz IR-UWB接收机的0.13μm CMOS射频前端设计

本文中使用0.13μm CMOS工艺实现了一款应用于脉冲式超宽带无线电的接收机射频前端电路。由于使用了欠采样的接收机架构,接收机中不再具有混频过程。因此,低噪声放大器和可变增益放大器均需要直接处理宽带射频信号。为了优化噪声和线性度,低噪声放大器使用了具有电容交叉耦合的全差分共栅结构,在1.2V电源下仅消耗了1.8mA电流。低噪声放大器之后,一个具有两级结构的电流引导型可变增益放大器被用来实现增益调节功能。同时,低噪声放大器和两级可变增益放大器共同构成了一个三级参差峰化网络,以提高接收机的总体带宽。测试结果表明,该射频前端模块在6-7GHz带宽内实现了5-40dB的增益调节范围,最小噪声系数和最大输入三阶交调分别达到了4.5dB和-11dBm。电路总体功耗为14mW,使用1.2V电源电压,核心部分芯片面积为0.58mm2.     

多模多频收发机中可编程增益放大器的设计

设计了一种基于运算放大器和电阻反馈网络的宽带全差分可编程增益放大器.该可编程增益放大器(PGA)采用三级级联结构,实现增益为1～57 dB可变,步长为2 dB.PGA中运放采用零点补偿法扩展带宽,整个PGA带宽达30 MHz.芯片采用IBM 0.13μm标准CMOS工艺实现,电源电压为2.5 V,功耗为62 mW.     

一种4GHz、23dB CMOS宽带限幅放大器的设计与实现

该文主要介绍了关于宽带限幅放大器在0.18μm CMOS工艺下的设计与实现,该宽带限幅放大器在第二次流片中采用了反比例级联结构、有源电感负载以及添加输出缓冲级技术来保证展宽带宽以及保证整个放大器的稳定性.最后所得测试结果为23dB增益,4GHz 3dB带宽.     

低功耗恒定带宽可编程增益放大器的设计

随着无线智能终端功能的不断丰富,可穿戴设备、无线传感器网络、无线手持终端等得到了快速发展,如何降低射频收发机的功耗成为了越来越突出的问题。作为射频收发机重要模块的可变增益放大器,其电路设计的好坏往往直接决定了射频接收机的总体性能,在此研究并设计一种低功耗恒定带宽可编程增益放大器,该可编程增益放大器主要由2个Gm跨导单元、压控电流衰减器以及电阻阵列构成。采用两个高线性度Gm跨导单元有效减小芯片面积和功耗,并且增益变化不会导致带宽变化。在TSMC 130 nm CMOS工艺下进行了后仿真验证,实验结果显示该可编程增益放大器在1.2 V电源电压下以400μA的电流消耗实现了增益调节范围0~40 d B,增益连续调节,线性度OIP3为18.84 d B,性能良好。     

0.2 GHz～3.2 GHz超宽带低噪声放大器的研制

为了降低接收前端的噪声,设计并制作一种超宽带低噪声放大器。基于负反馈技术和宽带匹配技术,利用Avago ATF-54143 PHEMT晶体管设计了放大器电路。运用ADS2009对重要指标进行仿真及优化。实测结果表明,在0.2 GHz～3.2 GHz这4个倍频程的超宽带范围内,增益大于24 dB,增益平坦小于±2 dB。在0.2 GHz～2GHz内,噪声系数（NF）小于1.2 dB;在2 GHz～2.6 GHz内,NF〈1.5 dB;在2.6 GHz～3.2 GHz内,NF〈2 dB。该放大器性能良好,满足工程应用要求,可用于通信系统的接收机前端。     

应用于SC-UWB收发机的CMOS射频接收前端电路设计

设计了应用于单载波超宽带（SC-UWB）无线收发机中的CMOS射频接收前端电路. 该前端电路采用直接变频结构,包含一个差分低噪声放大器（LNA）、一个正交混频器和两个中频放大器。其中,LNA采用源级电感负反馈结构.首先给出了该类型LNA中输入匹配带宽关于栅源电容、工作频率及匹配目标值的表达式 然后考虑到栅极片上电感、键合电感及其精度,提出了在增益和功耗约束下的噪声因子优化策略。该LNA利用两级放大级的不同谐振点实现了7.1~8.1GHz频段上的平坦增益,并具有两种增益模式来改善接收机动态范围. 正交混频器采用折叠式双平衡吉尔伯特结构. 该射频前端电路采用TSMC0.18um RF CMOS工艺设计,芯片面积为1.43 mm2. 在高、低增益模式下,测得的最大转换增益分别为42dB和22dB,输入1dB压缩点为-40dBm和-20dBm,S11低于-18dB和-14.5dB,中频3dB带宽大于500MHz. 高增益模式下双边带噪声因子为4.7dB. 整个电路在1.8V供电电压下功耗为65mW。     

2.5Gb/s宽动态范围光接收机前端放大电路设计

基于UMC 0.18μm CMOS工艺,设计了一种2Gb/s传输速率的宽动态范围光接收机前端放大电路。采用对数放大器来增大接收机的输入动态范围,前置放大器采用差分共源跨阻放大器,并使用有源电感做负载来增大带宽。实验结果表明:该接收机前端电路的增益为80dB,3dB带宽为2.3GHz,2.5Gb/s输出眼图良好,输入动态范围为60dB(1μA～1mA)。     

一种应用于DRM/DAB/DVB-H的噪声抵消和IP3改进的CMOS射频前端设计

本文给出了一种应用于数字广播标准的CMOS射频前端电路芯片,其包括宽带低噪声放大器、正交混频器和可变增益放大器,该前端能够支持200kHz-2GHz频率范围内的多种无线通信标准,该电路在没有牺牲其他电路性能包括电压增益和功耗的情况下,改善了NF和IP3。通过噪声抵消技术降低前端的NF,通过差分多栅晶体管结构（DMGTR）提高前端的IP3。dB线性可变增益放大器的增益控制通过采用工作在线性区的PMOS晶体管来实现。芯片采用0.18um CMOS工艺实现。测试结果表明在200kHz-2GHz范围内S11小于-11.4,增益变化范围在250MHz为12-42dB,在2GHz为4-36dB。单边带NF为3.1-6.1 dB。在中等增益情况下IIP3为-4.7-2.0dBm。整个前端在1.8V电源电压情况下功耗仅仅为36mW。     

一种用于3.1–4.8GHz MB-OFDM 超宽带系统的CMOS接收机

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的全集成全差分CMOS接收机芯片。在接收机射频前端中应用了一种增益可变的低噪声放大器和合并结构的正交混频器。在I/Q中频通路中则集成了5阶Gm-C结构的有源低通滤波器以及可变增益放大器。芯片通过Jazz 0.18μm RF CMOS工艺流片,含ESD保护电路。该接收机最大电压增益为65dB,增益可调范围为45dB,步长6dB;接收机在3个频段的平均噪声系数为6.4-8.8dB,带内输入三阶交调量(IIP3)为-5.1dBm。芯片面积为2.3平方毫米,在1.8V电压下,包括测试缓冲电路和数字模块在内的总电流为110mA。     

3．1～10．6GHz超宽带低噪声放大器的设计

基于SIMC0．18μmRFCMOS工艺技术,设计了可用于3．1—10．6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器（LNA）。该LNA采用三级结构：第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明：在电源电压为1．8v的条件下,所设计的LNA在3．1～10．6GHz的频带范围内增益（521）为20dB左右,具有很好的增益平坦性f±0．4dB）,回波损耗S11、S22均小于-10dB,噪声系数为4．5dB左右,IIP3为-5dBm,PIdB为0dBm。     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

A Fully Integrated 60GHz Four Channel CMOS Receiver with 7GHz Ultra-Wide Bandwidth for IEEE 802.11ad Standard

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.     

具有30dB增益和1-16GHz带宽的CMOS低噪声中频放大器

This paper presents a high-gain wideband low-noise IF amplifier aimed for the ALMA front end system using 90-nm LP CMOS technology.A topology of three optimized cascading stages is proposed to achieve a flat and wideband gain.Incorporating an input inductor and a gate-inductive gain-peaking inductor,the active shunt feedback technique is employed to extend the matching bandwidth and optimize the noise figure.The circuit achieves a flat gain of 30.5 dB with 3 dB bandwidth of 1-16 GHz and a minimum noise figure of 3.76 dB.Under 1.2 V supply voltage,the proposed IF amplifier consumes 42 mW DC power.The chip die including pads takes up 0.53 mm~2,while the active area is only 0.022 mm~2.     

应用于S波段AESA的射频收发前端设计

采用0．18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3．3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5．0dBm,射频输出在2～3．5GHz频带内电压增益为6．3～9．2dB,噪声系数小于14．5dB;接收前端工作电流为50mA,输入1dB压缩点为-5．6dBm,射频输入在2～3．5GHz频带内电压增益为12—14．5dB,噪声系数小于11dB;所有端口电压驻波比均小于1．8：芯片面积1．8×2．6mm0。     

CMOS超宽带低噪声放大器的设计

由于超宽带技术能够在短距离内传输几百兆的数据,帮助人们摆脱对导线的依赖,因此使得大带宽数据的无线传输从几乎不可能变为现实。尽管目前超宽带技术的标准还没有统一,但是低噪声放大器终归是其接收机中一个不可或缺的重要模块。文章介绍了一种基于0.18μmCMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器。结合计算机辅助设计,该超宽带低噪声放大器输入、输出均实现良好的阻抗匹配,在3GHz～10GHz的频带范围内实现了增益G=29±1dB,噪声系数小于4dB。在1.8V工作电压下放大器的直流功耗约为35mW。     

220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。     

A 0.18 μm CMOS TIA Plus Limiting Amplifier with a 5.3 GHz Overall Bandwidth for Fiber Optic Communications

A shunt series feedback transimpedance amplifier (TIA), based on a current amplifier using a zero–pole cancellation, followed by a 6 stages limiting amplifier (LA), proves to be suitable as receiver front-end for a 8 Gb/s communications over fiber optic. The front-end is realized with a 0.18 μm CMOS technology, and shows the following performances: the TIA has a 50 dBΩ transimpedance gain and 5.5 GHz bandwidth, the LA has a 46 dB gain and 7.9 GHz bandwidth. The differential voltage swing at the output is 300 mV. The total power consumption is 112 mW.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

Design of a Noise-Canceling CMOS Wideband Receiver Front-End with Inherent Active Balun

This paper presents the design of an ESD-protected noise-canceling CMOS wideband receiver front-end for cognitive and ultra-wideband (UWB) radio-based wireless communications. Designed in a 0.13-μm CMOS technology, the RF front-end integrates a broadband low-noise amplifier (LNA) and a quadrature down-conversion mixer. While having ESD and package parasitics absorbed into a wideband input matching network, the LNA exploits a combination of a common-gate (CG) stage and a common-source (CS) stage to cancel the noise of the CG-stage and to provide a well balanced differential output for driving the double-balance mixer, which has a merged quadrature topology. A variable-gain method is developed for the LNA to achieve a large factor of gain switch without degrading the input impedance match and the balun function. Drawing 24 mA from 1.5 V, simulations show that the proposed front-end has a 3-dB bandwidth of around 10 GHz spanning from 1.8 GHz up to 11.8 GHz with a maximum voltage conversion gain of 30 dB and a noise figure of 4.3–6.7 dB over the entire band.