对称三材料双栅应变硅MOSFET亚阈值电流与亚阈值斜率解析模型

基于泊松方程和边界条件,推导了对称三材料双栅应变硅金属氧化物半导体场效应晶体管（MOSFET：metal oxide semiconductor field effect transistor）的表面势解析解.利用扩散-漂移理论,在亚阈值区电流密度方程的基础上,提出了亚阈值电流与亚阈值斜率二维解析模型.分析了沟道长度、功函数差、弛豫SiGe层的Ge组份、栅介质层的介电常数、应变硅沟道层厚度、栅介质高k层厚度和沟道掺杂浓度等参数对亚阈值性能的影响,并对亚阈值性能改进进行了分析研究.研究结果为优化器件参数提供了有意义的指导.模型解析结果与DESSIS仿真结果吻合较好.     

垂直隧穿场效应晶体管的亚阈值特性分析

Subthreshold characteristics of vertical tunneling field effect transistors(VTFETs) with an nC-pocket in the pC-source are studied by simulating the transfer characteristics with a commercial device simulator.Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations.Band diagram analysis shows that such a VTFET can be treated as a gate-controlled tunnel diode connected in series with a conventional n-channel metal-oxide-semiconductor FET.This VTFET can work either as a TFET or an n-MOSFET in the subthreshold region,depending on the turn-on sequence of these two components.To our knowledge,this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid.Our results indicate that the design of the nC pocket is crucial for such a VTFET in order to achieve ultra-steep turn-on characteristics.     

An analytical threshold voltage and subthreshold current model forshort-channel MESFETs

Short-channel effects on the subthreshold behavior are modeled in self-aligned gate MESFETs with undoped substrates through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of the short-channel effects in MESFETs with doped and undoped substrates indicates that channel lengths will be limited to 0.15-0.2 μm by subthreshold conduction. Besides offering insight into the device physics of the short-channel effects in MESFETs, the model provides a useful basis for accurate analysis and simulation of small-geometry GaAs MESFET digital circuits     

Analytical threshold voltage and subthreshold swing model for TMG FinFET

An analytical modelling of the subthreshold surface potential, threshold voltage (V_T) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and V_T models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate.     

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.     

一种带有斜向扩展源的双栅隧穿场效应晶体管

设计并研究了一种带有轻掺杂漏(LDD)和斜向扩展源(OES)的双栅隧穿场效应晶体管(DG-TFET),并利用Sentaurus TCAD仿真工具对栅长及扩展源长度等关键参数进行了仿真分析。对比了该器件与传统TFET的亚阈值摆幅、关态电流和开关电流比,并从器件的带带隧穿概率分析其优势。仿真结果表明,该器件的最佳数值开关电流比及亚阈值摆幅分别可达3.56×10¹²和24.5 mV/dec。另外,该DG-TFET在双极性电流和接触电阻方面性能良好,且具有较快的转换速率和较低的功耗。     

New optimized Dual-Material (DM) gate design to improve the submicron GaN-MESFETs reliability in subthreshold regime

In this paper, new Dual-Material-gate (DM) concept and optimization approach are proposed to improve the device immunity against the hot carrier and short channel effects (SCEs), and optimize the subthreshold electrical performance of the submicron Gallium Nitride (GaN)-MESFET. The 2D analytical analysis includes the modeling of the channel potential, subthreshold swing, threshold voltage, Drain-Induced Lowering Barrier (DIBL) and parasitic resistances. The influence of gate length and the work function of each gate region on subthreshold behavior was investigated using the developed analytical models. The developed analytical approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. The presented compact models are used to formulate the different objective functions, which are the pre-requisite of multi-objective genetic algorithms optimization, which will be used to optimize the device subthreshold performances. The optimized design can alleviate the critical problem and further improve the immunity of SCEs of submicron GaN-MESFET-based digital circuits for low power and high speed applications.     

An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs

An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Two-dimensional Poisson equation is solved analytically using series method and channel potential is obtained. The analytical expression for subthreshold swing is achieved. Model results are compared with Medici simulation results, both of them turn out to agree very well. The results show the variation of channel potential and subthreshold swing with channel length, gate bias, and oxide thickness, which will provide some guidance for the integrated circuit designs.     

An analytical threshold voltage and subthreshold current model forshort-channel AlGaAs/GaAs MODFETs

Short-channel effects on the subthreshold behavior are modeled in self-aligned gate AlGaAs/GaAs MODFETs through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of short-channel effects in enhancement-mode MODFETs with and without i-AlGaAs spacer layers indicates that channel lengths will be limited to 0.18-0.25 μm by subthreshold conduction. Minimum gate lengths for MODFETs with a spacer layer are notably larger than those without a spacer layer. Besides offering insights into the physics of short-channel effects in MODFETs, the model provides a useful basis for efficient design, analysis, and simulation of small geometry AlGaAs/GaAs MODFET digital circuits     

Physical subthreshold MOSFET modeling applied to viable design ofdeep-submicrometer fully depleted SOI low-voltage CMOS technology

An insightful study of the subthreshold characteristics of deep-submicrometer fully depleted SOI MOSFET's, based on two-dimensional numerical (PISCES) device simulations, shows that the gate swing and off-state current are governed by gate bias-dependent source/drain charge sharing, which controls back-channel as well as front-channel conduction. The insight from this study guides the development of a physical, two-dimensional analytic model for the subthreshold current and charge, which is linked to our strong-inversion formalism in SOISPICE for circuit simulation. The model is verified by PISCES simulations of scaled devices. The utility of the model in SOISPICE is demonstrated by using it to define a viable design for deep-submicrometer fully depleted SOI CMOS technology based on simulated speed and static power in low-voltage digital circuits     

Modeling the subthreshold swing in MOSFET's

This letter reports on the bias-dependence of the inverse subthreshold slope or subthreshold swing in MOSFET's. It is shown by calculations and verified by experiments that the subthreshold swing varies with gate bias and exhibits a global minimum. The gate-source voltage for which minimum subthreshold swing is reached, is linearly related to the voltage at which moderate inversion starts. Influence of oxide thickness and temperature is investigated. The subthreshold swing is an important parameter in modeling the weak inversion regime, especially for high-gain analog applications, imaging circuits, and low-voltage applications. Based on calculations of the subthreshold swing, we propose a new model for the diffusion component of the drain leakage current in MOSFET's. The model accurately predicts the temperature dependence of the drain leakage current     

Analysis of subthreshold carrier transport for ultimate DGMOSFET

A novel transport model for the subthreshold mode of double-gate MOSFETs (DGMOSFETs) is proposed in this paper. The model enables the analysis of short-channel effects (SCEs) such as the subthreshold swing (SS), the threshold-voltage rolloff, and the drain-induced barrier lowering. The proposed model includes the effects of thermionic emission and the quantum tunneling of carriers through the source-drain barrier. An approximative solution of the two-dimensional Poisson equation is used for the distribution of the electric potential, and the Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The model is verified by comparing the SS with numerical simulations. The new model is used to investigate the subthreshold characteristics of a DGMOSFET having the gate length in the nanometer range with an ultrathin gate oxide and channel thickness. The SCEs degrade the subthreshold characteristics of DGMOSFETs when the gate length is reduced below 10 nm, and any design in the sub-10-nm-regime should include the effects of quantum tunneling.     

Analysis of 14nm technology node In0.53Ga0.47As nFinFET integrated with In0.52Al0.48As cap layer for high-speed circuits

CMOS (Complementary Metal-oxide-semiconductor) based high-speed applications in the sub-14 nm technology node using InGaAs Fin field-effect-transistors (FinFETs) confront with inevitable effect in form of interface traps upon integration of dielectric layer with InGaAs material. In this work, we have explored the impact of the traps on short channel effects (SCEs) and a technique of abating the effect of interface traps by introducing In_0.52Al0.₄₈As cap layer. Proposed work reforms the device by varying the cap layer thickness (Tcap), doping concentrations of cap layer and underlap region. The effect of traps on intrinsic delay, work function variation and SCEs was investigated to assess the trend on devices with In_0.52Al_0.48As cap layer. It has been observed that introduction of Tcap improves SCEs and helps to mitigate the effect of interface traps. SCEs can be additionally diminished by presenting underlap fin length at the cost of higher delay. The experimental results show the value of subthreshold swing = 149.54 mV/decade, drain-induced barrier lowering = 38.5 mV V^?1 and delay = 1.1 ps for T_cap = 4 nm without underlap fin length structure for traps concentration of 10¹² cm^?2eV^?1. Thus, significant improvement has been seen in SCEs and delay performance in FinFET structure with cap layer.     

An optimized junctionless GAA MOSFET design based on multi-objective computation for high-performance ultra-low power devices

An analytical investigation has been proposed to study the subthreshold behavior ofjunctionless gates all around （JLGAA） MOSFET for nanoscale CMOS analog applications. Based on 2-D analytical analysis, a new subthreshold swing model for short-channel JLGAA MOSFETs is developed. The analysis has been used to calculate the subthreshold swing and to compare the performance of the investigated design and conventional GAA MOSFET, where the comparison of device architectures shows that the JLGAA MOSFET exhibits a superior performance with respect to the conventional inversion-mode GAA MOSFET in terms of the fabrication process and electrical behavior in the subthreshold domain. The analytical models have been validated by 2-D numerical simulations. The proposed analytical models are used to formulate the objectives functions. The overall objective function is formulated by means of a weighted sum approach to search the optimal electrical and dimensional device parameters in order to obtain the better scaling capability and the electrical performance of the device for ultra-low power applications.     

Double gate-MOSFET subthreshold circuit for ultralow power applications

In this paper, we propose MOSFETs that are suitable for subthreshold digital circuit operations. The MOSFET subthreshold circuit would use subthreshold leakage current as the operating current to achieve ultralow power consumption when speed is not of utmost importance. We derive the theoretical limit of delay and energy consumption in MOSFET subthreshold circuit, and show that devices that have an ideal subthreshold slope are optimal for subthreshold operations due to the smaller gate capacitance, as well as the higher current. The analysis suggests that a double gate (DG)-MOSFET is promising for subthreshold operations due to its near-ideal subthreshold slope. The results of our investigation into the optimal device characteristics for DG-MOSFET subthreshold operation show that devices with longer channel length (compared to minimum gate length) can be used for robust subthreshold operation without any loss of performance. In addition, it is shown that the source and drain structure of DG-MOSFET can be simplified for subthreshold operations since source and drain need not be raised to reduce the parasitic resistance.     

A new two-dimensional subthreshold behavior model for the short-channel asymmetrical dual-material double-gate (ADMDG) MOSFET’s

Based on the exact solution of two-dimensional Poisson’s equation, a novel subthreshold behavior model comprising channel potential, subthreshold swing, and threshold voltage for the short-channel asymmetrical dual-material double-gate (ADMDG) MOSFET’s have been developed. The model is verified by its simulation results that agree well with those of the two-dimensional numerical simulator. Besides offering the physical insight into device physics, the model provides the basic designing guidance for the ADMDG MOSFET’s.     

绝缘体上硅FinFET亚阈值摆幅研究

在新型多栅器件栅电容模型的研究中,量子电容随着沟道长度及栅氧化层厚度的不断减小而变得越发不可忽略。推导了基于绝缘体上硅(SOI)工艺技术的鳍式场效应晶体管(FinFET)的量子电容,并通过构建囊括量子电容的内部电容网络模型推导了亚阈值摆幅。采用Matlab软件,仿真验证了量子电容对亚阈值摆幅的影响。提出了亚阈值摆幅的优化方法,为如何选取合适的器件尺寸来优化某个特定设计目标的性能提供了指导。     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管,并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路,但是在有源扩展区部分,由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ≈78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a ±10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (≈40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.     

Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs

The subthreshold swing and threshold voltage characteristics of multiple-gate SOI transistors have been numerically simulated. These devices behave like cylindrical, surrounding gate devices, with the exception of the corner inversion effect. The corner inversion effect is, however, shown to be negligible if the devices are fully depleted devices or if the gate insulator thickness is small enough.