纳米晶存储特性的研究

常温下硅纳米晶构成的MOSFET存储器具有低压、低功耗、体积小、高剂量和快速读写等优良特性,在ULSI中有重要的应用前景.它是当前ULSI研究中的一项热门专题,在国外一些著名刊物上屡见报道.本文介绍了这种器件的存储特性及其机理与最新研究进展.     

硅纳米晶的制备和电荷储存特性

在Si/SiO2/Si衬底上通过真空热处理生长了硅纳米晶,利用原子力显微镜对硅纳米晶注入电荷,在静电力模式下研究了硅纳米晶的充放电特性.实验结果表明,硅纳米颗粒充电后电荷可以保存10h以上,同时可以在几秒内快速放电.电荷储存于纳米颗粒内部和表面,不会向外扩散.     

硅纳米晶的制备和电荷储存特性

在Si/SiO2/Si衬底上通过真空热处理生长了硅纳米晶,利用原子力显微镜对硅纳米晶注入电荷,在静电力模式下研究了硅纳米晶的充放电特性．实验结果表明,硅纳米颗粒充电后电荷可以保存10h以上,同时可以在几秒内快速放电．电荷储存于纳米颗粒内部和表面,不会向外扩散．     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

基于硅纳米晶的非挥发存储器制备与存储特性

硅纳米晶非挥发存储器由于其卓越的性能以及与传统工艺的高度兼容性,近来引起高度关注。采用两步低压化学气相淀积(LPCVD)生长方式制备硅纳米晶(Si-NC),该方法所制备的硅纳米晶具有密度高、可控性好的特点,且完全兼容于传统CMOS工艺。在此基础上制作四端硅纳米晶非挥发存储器,该器件展示出良好的存储特性,包括10 V操作电压下快速地擦写,数据保持特性的显著提高,以及在105次擦写周期以后阈值电压(Vt)飘移低于10%的良好耐受性。该器件在未来高性能非挥发存储器应用上极具潜质。     

高能球磨法制备纳米钛酸钡的晶化过程

利用高能球磨法,无后续煅烧,以二氧化钛和过氧化钡为原料,在室温下4h制备出单相纳米钛酸钠粉。利用XRD图谱结合Sherre公式研究了球磨过程中纳米钛酸钡的晶化过程。结果表明,所制备的钛酸钡结晶情况良好,为立方钙钛矿结构,在球磨过程中钛酸钡晶粒呈现出先逐渭长大然后逐渐减小的趋势,经透射电镜观察,球磨8h所得钛酸钡晶粒尺寸为18－22nm。     

Ni纳米晶制备及其在MOS电容中存储特性研究

优化了Ni纳米晶的制备工艺参数,得到了分布均匀,形状为球形,平均尺寸5nm,密度2×1012/cm2的Ni纳米晶。在此基础上,制备了包含Ni纳米晶的MOS电容结构。利用高频电容-电压(C-V)和电导-电压(G-V)测试研究了其电学性能,证明该MOS电容结构的存储效应主要源于金属纳米晶的限制态。电容-时间(C-t)测试曲线呈指数衰减趋势,保留时间600s,具有较好的保留性能。     

镍硅化物诱导横向晶化制备高性能多晶硅薄膜晶体管

提出一种新的采用镍硅化物作为种子诱导横向晶化制备低温多晶硅薄膜晶体管的方法。分别采用微区Raman、原子力显微镜和俄歇电子能谱对制备的多晶硅薄膜进行结构和性能表征,并以此多晶硅薄膜为有源层制备了薄膜晶体管,测试其I-V转移特性。测试结果显示,制备的多晶硅薄膜具有较低的金属污染和较大的晶粒尺寸,且制备的多晶硅薄膜晶体管具有良好的电学特性,可以有效地减小漏电流,同时可提高场效应载流子迁移率。这主要是由于多晶硅沟道区中镍含量的有效降低使得俘获态密度减少。     

基于不同测量手段的纳米晶器件的存储特性

对纳米晶器件,尤其是MOS电容进行了横截面TEM分析和不同条件下的电学特性(C-V特性)测量,包括+/-BT分析. 揭示了系统的纳米晶存储物理机制,例如电荷俘获、界面态填充和温度特性. 研究结果表明,高温、大电压摆幅和偏置情况下,器件编程窗口的恶化和阈值电压的漂移与多数载流子的种类有关.     

基于不同测量手段的纳米晶器件的存储特性

对纳米晶器件,尤其是MOS电容进行了横截面TEM分析和不同条件下的电学特性(C-V特性)测量,包括 /-BT分析. 揭示了系统的纳米晶存储物理机制,例如电荷俘获、界面态填充和温度特性. 研究结果表明,高温、大电压摆幅和偏置情况下,器件编程窗口的恶化和阈值电压的漂移与多数载流子的种类有关.     

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO_2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

使用化学方法常温合成金纳米晶并通过旋涂工艺将其组装的存储特性可调型非易失性存储器

3C行业的不断发展,催生了对高密度、持久保存、快速擦写、鲁棒可靠性的非易失性存储器(如flash)的持续需求,促使我们在科研上不断地深入研究新材料、新工艺。在本文中,我们首次采用了区别于传统CMOS工艺的两步工艺方法来制作金属纳米晶非易失性存储器。这种方法,由于将金纳米晶的化学合成和后续组装分离开来,所以能够独立地调节纳米晶的尺寸和组装密度,而且可以很好地避免一直困扰的金属扩散问题。最终的形貌表征和电学测量结果,证实存在一个最优化的纳米晶密度--在这个最优化条件下,我们的存储器件,既有持久的保存时间,又有较大的存储窗口。而组装密度的可调,同时可以满足我们对于大的存储窗口/较长保存时间某一方面的偏好。这些实验结果,都很好地证明了我们两步工艺方法的可行性。     

Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique

A novel two-step method is employed,for the first time,to fabricate nonvolatile memory devices that have metal nanocrystals.First,size-averaged Au nanocrystals are synthesized chemically;second,they are assembled into memory devices by a spin-coating technique at room temperature.This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually.In addition,processes at room temperature prevent Au diffusion,which is a main concern for the application of...     

CH3NH3PbI3/p-Si异质结的光电特性研究

利用一步溶液法在p型Si衬底上生长有机/无机杂化钙钛矿CH3NH3PbI3薄膜,构成CH3NH3PbI3/p-Si异质结。利用原子力显微镜(AFM)、扫描电子显微镜(SEM)对薄膜形貌和结构进行表征,通过无光照和有光照条件下的电流-电压(I-V)、电容-电压(C-V)测试对异质结的光电特性进行研究。I-V测试结果显示CH3NH3PbI3/p-Si异质结具有整流特性,正反偏压为±5V时,整流比大于70,并在此异质结上观察到了光电转换现象,开路电压为10mV,短路电流为0.16uA。C-V测试结果显示Ag/CH3NH3PbI3/p-Si异质结具有与MIS(金属-绝缘层-半导体)结构相似的C-V特性曲线,与理想MIS的C-V特性曲线相比,异质结的C-V曲线整体沿电压轴向正电压方向平移。C-V特性曲线的这种平移表明Ag/CH3NH3PbI3/p-Si异质结界面存在界面缺陷,CH3NH3PbI3层也可能存在固定电荷。这种界面缺陷是导致CH3NH3PbI3/p-Si异质结开路电压的大幅度降低的重要原因。此外,CH3NH3PbI3薄膜的C-V测试结果显示其具有介电非线性特性,其介电常数约为4.64。     

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

A thin transition film formed by plasma exposure contributes to the germaniumsurface hydrophilicity

Plasma treatment and 10% NH₄OH solution rinsing were performed on a germanium (Ge) surface. It was found that the Ge surface hydrophilicity after O₂ and Ar plasma exposure was stronger than that of samples subjected to N₂ plasma exposure. This is because the thin GeO_x film formed on Ge by O₂ or Ar plasma is more hydrophilic than GeO_xN_y formed by N₂ plasma treatment. A flat (RMS<0.5 nm) Ge surface with high hydrophilicity (contact angle smaller than 3°) was achieved by O₂ plasma treatment, showing its promising application in Ge low-temperature direct wafer bonding.     

Capacitance-voltage analysis of a high-k dielectric on silicon

Device characteristics of TiO₂ gate dielectrics deposited by a sol-gel method and DC sputtering method on a P-type silicon wafer are reported. Metal-oxide-semiconductor capacitors with Al as the top electrode were fabricated to study the electrical properties of TiO₂ films. The films were physically characterized by using X-ray diffraction, a capacitor voltage measurement, scanning electron microscopy, and by spectroscopy ellipsometry. The XRD and DST-TG indicate the presence of an anatase TiO₂ phase in the film. Films deposited at higher temperatures showed better crystallinity. The dielectric constant calculated using the capacitance voltage measurement was found to be 18 and 73 for sputtering and sol-gel samples respectively. The refractive indices of the films were found to be 2.16 for sputtering and 2.42 for sol-gel samples.     

废旧镍氢电池溶胶–凝胶法制备Ni_(0.5)Co_(0.5)Fe_2O_4的研究

以硫酸溶解废旧镍氢电池所得溶液为原料,采用溶胶–凝胶法制备出纳米晶镍钴铁氧体。借助于XRD、TG和VSM对产品的相结构和磁性能进行研究,并进一步探讨制备过程中的影响因素。结果表明,溶胶–凝胶法制备镍钴铁氧体的适宜条件为:柠檬酸与金属离子总量的摩尔比1:1,溶液的pH值7.0,煅烧温度850℃,煅烧时间3 h。该条件下所制得产品的剩余磁化强度为13.635 A.m2/kg,矫顽力为32.5 kA/m,饱和磁化强度为50.713 A.m2/kg。     

Temperature dependent current–voltage (I–V) characteristics of Au/n-Si (1 1 1) Schottky barrier diodes with PVA(Ni,Zn-doped) interfacial layer

Current–voltage (I–V) characteristics of Au/PVA/n-Si (1 1 1) Schottky barrier diodes (SBDs) have been investigated in the temperature range 80–400 K. Here, polyvinyl alcohol (PVA) has been used as interfacial layer between metal and semiconductor layers. The zero-bias barrier height (Φ_B0) and ideality factor (n) determined from the forward bias I–V characteristics were found strongly dependent on temperature. The forward bias semi-logarithmic I–V curves for different temperatures have an almost common cross-point at a certain bias voltage. The values of Φ_B0 increase with the increasing temperature whereas those of n decrease. Therefore, we have attempted to draw Φ_B0 vs. q/2kT plot in order to obtain evidence of a Gaussian distribution (GD) of the barrier heights (BHs). The mean value of BH and standard deviation (σ₀) were found to be 0.974 eV and 0.101 V from this plot, respectively. Thus, the slope and intercept of modified vs. q/kT plot give the values of and Richardson constant (A^?) as 0.966 eV and 118.75 A/cm²K², respectively, without using the temperature coefficient of the BH. This value of A^* 118.75 A/cm²K² is very close to the theoretical value of 120 A/cm²K² for n-type Si. Hence, it has been concluded that the temperature dependence of the forward I–V characteristics of Au/PVA/n-Si (1 1 1) SBDs can be successfully explained on the basis of the Thermionic Emission (TE) theory with a GD of the BHs at Au/n-Si interface.