提高激光反馈扫描显微镜轴向分辨率的实验研究

提出并实验研究了几种可以提高激光反馈扫描显微镜轴向分辨率的方法，一种方法是对常规激光反馈实验中的探测技术进行了改进，用渥拉斯顿棱镜把垂直偏振光分开探测，轴向分辨率可以提高约2．9倍；另一种方法是用双频激光器中产生的偏振态相互垂直的O光和e光作为反馈光代替了传统的单一光的反馈，轴向分辨率被提高了约2倍；第三种方法是用双频激光器中产生的O光或e光作为反馈光，轴向分辨率可以提高约2．5倍。实验结果表明，利用偏振态相互垂直的光之间的模竞争效应可以有效地提高扫描显微镜的轴向分辨率。     

Scan Test Response Compaction Combined with Diagnosis Capabilities

As today’s process technologies are combined with ever increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities, in combination with the smaller feature sizes, require that we now address defect mechanisms that safely could be more or less ignored in earlier technologies. Scan based delay fault testing (AC-scan) enhances defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper, we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in Rajski et al., Convolutional compaction of test responses, 2003). Our scheme is diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Leininger et al., Compression mode diagnosis enables high volume monitoring diagnosis flow, 2005; Stanojevic et al., Enabling yield analysis with X-compact, 2005). Yet, the compactor has comparable performance to other schemes (Mitra et al., X-compact: an efficient response compaction technique, 2004; Mitra S et al., X-tolerant test response compaction, 2005; Rajski et al., Convolutional compaction of test responses, 2003) when it comes to ‘X’ tolerance and aliasing.     

Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells

While integrated circuits of ever increasing size and complexity necessitate larger test sets for ensuring high test quality, the consequent test time and data volume reflect into elevated test costs. Test data compression solutions have been proposed to address this problem by storing and delivering stimuli in a compressed format. The effectiveness of these techniques, however, strongly relies on the distribution of the specified bits of test vectors. In this paper, we propose a scan cell partitioning technique so as to ensure that specified bits are uniformly distributed across the scan slices, especially for the test vectors with higher density of specified bits. The proposed scan cell partitioning process is driven by an integer linear programming (ILP) formulation, wherein it is also possible to account for the layout and routing constraints. While the proposed technique can be applied to increase the effectiveness of any combinational decompression architecture, in this paper, we present its application in conjunction with a fan-out based decompression architecture. The experimental results also confirm the compression enhancement of the proposed methodology.

Isolation of Failing Scan Cells through Convolutional Test Response Compaction

This paper describes a non-recursive fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss–Jordan elimination method.

扫描单元及其在ASIC可测性设计中的应用

本文首先论述ＡＳＩＣ可测性的必要性,然后介绍了几种常见的扫描单元,最后给出了多种选择触发器方法、时钟扫描方法、电平敏感扫描方法等几种内部扫描方法。     

Construction and Analysis of Augmented Time Compactors

In this paper, a procedure for constructing time compactors based on a new 3-dimensional augmented product code is presented. Accordingly, augmented time compactors are constructed by assigning a unique triplet <x,y,z> to each scan chain and calculating at least four sets of parity check bits. Parity check bits of each set are XORed into stages of one or more multi-input shift registers. The proposed method allows constructing different classes of time compactors directly based on the coding theory. The constructed augmented time compactors outperform the most advanced time compactors of each respective class. All constructed compactor schemes are strictly defined and establish a clear baseline for future development in this area.     

提高共面转换液晶显示器件响应时间的研究

利用液晶弹性理论和动力学理论对共面转换液晶显示器件响应时间参数进行了分析, 将聚合物网络引入这种模式, 利用聚合物网络对液晶的锚定作用, 使得 Ｉ Ｐ Ｓ液晶显示器件的下降响应时间得到极大改善。实验结果表明, 聚合物的百分比含量对器件的响应时间、阈值电压、对比度有较大影响。     

Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique

Power consumption during scan testing operations can be significantly higher than that expected in the normal functional mode of operation in the field. This may affect the reliability of the circuit under test (CUT) and/or invalidate the testing process increasing yield loss. In this paper, a scan chain partitioning technique and a scan hold mechanism are combined for low power scan operation. Substantial power reductions can be achieved, without any impact on the test application time or the fault coverage and without the need to use scan cell reordering or clock and data gating techniques. Furthermore, the proposed design solution for scan power alleviation, permits the efficient exploitation of X-filling techniques for capture power reduction or the use of extreme (power independent) compression techniques for test data volume reduction.     

扫描测试和扫描链的构造

本文首先论述了扫描设计与测试向量自动生成（ATPG）这种测试方法的关键技术，并由此为依据，提出部分扫描设计中，扫描链构造的分层次的三个选取原则。     

INS/GPS Integration: Global Observability Analysis

Observability is an important aspect of the state-estimation problem in the integration of the inertial navigation system (INS) and the Global Positioning System (GPS) as it determines the existence and nature of solutions. In most previous research, conservative observability concepts, e.g., local observability and linear observability, have extensively been used to locally characterize the estimability properties. In this paper, a novel approach that directly starts from the basic observability definition is used to investigate the global observability of the nonlinear INS/GPS system with consideration of the lever arm uncertainty. A sufficient condition for the global observability of the system is presented. Covariance simulations with an extended Kalman filter (EKF) and a field test are performed to confirm the theoretical results. The global observability analysis approach is not only straightforward and comprehensive but also provides us with new insights that were unreachable by conventional methods.      

提高燃料电池测试设备抗EMI能力的应用研究

电子设备的电磁兼容性指标已成为电子设备在研制时的一个重要的技术要求。燃料电池的各种性能测试过程中所用到的燃料电池测试设备,由于涉及到气体控制、液体控制和电路控制等多种技术领域,引起不同的控制部件之间存在着比较严重的的电磁干扰现象,因此,在燃料电池测试设备的系统设计时需要全面考虑电磁兼容性问题。在介绍燃料电池测试设备的系统概况的同时,详细介绍了燃料电池测试设备在系统设计中采用电磁兼容技术,提高抗电磁干扰能力的各种方法和措施。     

Balanced Secure Scan: Partial Scan Approach for Secret Information Protection

Scan-based Design-for-Testability technique is widely used to enhance the testability. However, it increases the vulnerability to attacks through scan chains for secure chips such as cryptographic circuits with embedded secret keys. This paper proposes a secure scan design method which protects the circuits containing secret information such as cryptographic circuits from scan-based side channel attacks. The proposed method prevents the leakage of secret information by partial scan design based on a balanced structure. We also guarantee the testability of both the design under test and DFT circuitry, and therefore, realize both security and testability. Experiments for RSA circuit shows the effectiveness of the proposed method.     

主动段弹道估计可观测性分析

空间红外预警系统仅可获得弹道导弹主动段尾焰辐射信号方位角信息，采用极大似然估计和非线性最小二乘估计可获得目标运动状态的迭代解。预警卫星与目标距离较远，测量方程非线性，可观测性较弱。本文即从估计误差CRLB和Fisher信息矩阵条件数入手，对弹道导弹目标主动段状态估计可观测性做出理论推导和仿真分析。     

Observability of decoupled time-varying multivariable systems

The decoupling of a time-varying multivariable system by state-variable feedback does not guarantee the observability of the decoupled system. In the letter, a necessary and sufficient condition is derived for the observability of these systems in the time-variable case.     

多链扫描可测性设计中扫描链的选取

本文提出了多链扫描可测性设计中扫描链的构造方法．根据电路的规模、输人／输出管脚数及测试时间的要求确定扫描链个数，引人临界时间的概念，采用动态编程的方法确定每条链中的扫描触发器．采用该方法，计算速度比传统方法显著提高，同时节省了存储空间．     

Observability of permutations, and stream ciphers

We study the observability of a permutation on a finite set by a complex-valued function. The analysis is done in terms of the spectral theory of the unitary operator on functions defined by the permutation. Any function f can be written uniquely as a sum of eigenfunctions of this operator; we call these eigenfunctions the eigencomponents of f. It is shown that a function observes the permutation if and only if its eigencomponents separate points and if and only if the function has no nontrivial symmetry that preserves the dynamics. Some more technical conditions are discussed. An application to the security of stream ciphers is discussed.     

方位-到达时间联合TMA的可测性分析

针对在三维空间做匀速运动的目标,应用非线性系统的可测性理论,对方位-到达时间TMA(目标运动分析)的可测性进行了分析.基于方位和到达时间方法的单站无源定位技术,是通过观测站接收目标辐射源两次TOA(脉冲到达时间)测量之间由于目标运动所造成目标与观测站之间的径向距离发生变化的信息,对目标进行定位.结果表明在观测站与辐射源间的方位角和俯仰角变化率不能同时为零的情况下,观测机不必做机动就可以实现观测.     

A Method of Improving the Response of Waveguide Directional Couplers (Correspondence)

This communication describes a technique for decreasing the frequency variation of coupling of multihole broadwall waveguide directional couplers. The usual curve of coupling vs frequency is shown in Fig. 1 and has a peak-to-peak variation of 1.0 db. The proposed method, which is similar to the use of multiple sections in coaxial couplers, perturbs the coupled voltage by adding a small voltage that is in phase at midband where the coupling is looser and out of phase near the band edges. The required perturbation is produced by means of the coupling structure shown in Fig. 2, where the phase of one coupled voltage is delayed with respect to the other coupled voltage because of an added path length /spl Delta/L.     

Eliminating the Timing Penalty of Scan

Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a pair of scan cell transformation techniques that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. The first technique is an ad-hoc technique, while the second one is the retiming technique applied on the scan logic. The proposed transformation techniques retain the test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan in a cost-effective way and thus enhancing the functional speed of integrated circuits.     

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra hardware cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant test time reduction in comparison with state-of-the-art Boundary Scan test tecnique.