Construction and Analysis of Augmented Time Compactors

In this paper, a procedure for constructing time compactors based on a new 3-dimensional augmented product code is presented. Accordingly, augmented time compactors are constructed by assigning a unique triplet <x,y,z> to each scan chain and calculating at least four sets of parity check bits. Parity check bits of each set are XORed into stages of one or more multi-input shift registers. The proposed method allows constructing different classes of time compactors directly based on the coding theory. The constructed augmented time compactors outperform the most advanced time compactors of each respective class. All constructed compactor schemes are strictly defined and establish a clear baseline for future development in this area.     

On minimizing aliasing in scan-based compaction

In this article we address the problem of compacting test response data captured in scan paths. We consider linear compactors, e.g., multiple-input signature registers, and the effect of their characteristic polynomials on the number of aliased faults. The novelty of our analysis lies in that it is based on a realistic error model which takes into account the time correlation among the errors in the test response data fed to the compactor. Such a correlation does exist in scan-based compaction, but has not been considered previously. Based on our analysis, we derive three conditions that should be satisfied to minimize aliasing. They impose little restriction on circuit design.This work was supported in part by grants from the Natural Sciences and Engineering Research Council of Canada and in part by the British Columbia Advanced Systems Institute.     

Scan Test Response Compaction Combined with Diagnosis Capabilities

As today’s process technologies are combined with ever increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities, in combination with the smaller feature sizes, require that we now address defect mechanisms that safely could be more or less ignored in earlier technologies. Scan based delay fault testing (AC-scan) enhances defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper, we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in Rajski et al., Convolutional compaction of test responses, 2003). Our scheme is diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Leininger et al., Compression mode diagnosis enables high volume monitoring diagnosis flow, 2005; Stanojevic et al., Enabling yield analysis with X-compact, 2005). Yet, the compactor has comparable performance to other schemes (Mitra et al., X-compact: an efficient response compaction technique, 2004; Mitra S et al., X-tolerant test response compaction, 2005; Rajski et al., Convolutional compaction of test responses, 2003) when it comes to ‘X’ tolerance and aliasing.     

Exploiting distribution of unknown values in test responses to optimize test output compactors

Test output compactors can effectively reduce the data volume of test responses without scarifying fault coverage. However, when there are unknown values (X-bits) in the test output, the fault coverage can be severely comprised. Many compaction schemes that can handle X-bits have been developed. However, existing test response compaction schemes are designed without considering the locations of errors and X-bits. This design methodology essentially assumes that observable errors as well as X-bits are randomly distributed among all scan cells. Recent studies show that X-bits may not be randomly distributed; some scan cells could capture much more X-bits than others. In this paper, we propose to exploit the nonuniform distribution of X-bits to optimize test response compactors such that a higher compression rate is achieved with lower hardware overhead. The proposed design method is applicable to various test output compaction schemes that can handle X-bits in the test responses, including X-blocking, X-masking, and X-tolerant circuits. Experimental results show that, in the presence of X-bits, the compression results will be significantly improved with the help of the proposed method.     

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs

This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal—spatial and time—signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.     

Design, Analysis, and Experimentation of Chaotic Permanent Magnet DC Motor Drives for Electric Compaction

In this brief, a new electrically chaotic permanent magnet dc motor drive is designed, analyzed, and implemented for electric compaction. The key is to newly apply chaotic speed reference control to the torque controller of the motor drive, which, in turn, generates chaotic motion for the compactor. The proposed electric chaoization not only offers the advantages of lighter weight, smaller size, and higher controllability, compared with its mechanical counterpart, but also provides higher flexibility and better accuracy, compared with previous electric chaoizing approaches. By numerically comparing the compaction performance, i.e., the average compaction energy density, the proposed chaotic compactor is more effective than the conventional compactors using constant input voltage control and sinusoidal speed reference control. After prototyping, experimentation is performed to verify the validity of the proposed compactor.      

On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power

Scan-based testing of integrated circuits results in significant switching activity during the shift operations, dissipating excessive power levels. When such levels are beyond the peak power level under which the chip can functionally operate at, it may lead to an unexpected behavior of the design, resulting in a yield loss. One of the most effective solutions to reduce peak shift power is to partition the scan chains into multiple groups, wherein a single group is active at any time instance within a shift cycle. The partitioning of the chains into groups can be performed statically, i.e., per test set, or dynamically, i.e., per test pattern. In this work, we address the application of dynamic scan chain partitioning for reducing peak shift power. First, we address the application of dynamic partitioning to test delay faults in at-speed test techniques. Then, we formulate the scan chain partitioning problem via Integer Linear Programming (ILP), in order to evenly distribute the transitions produced by any pattern over multiple time instances within the shift cycle, maximally reducing the peak shift power. Finally, we evaluate the power reduction benefit of dynamic partitioning through an extensive set of experiments using different scan configurations and test set characteristics of benchmark circuits as well as industrial designs. The results indicate that dynamic partitioning provides significant reduction to peak shift power over static partitioning methods, and that the benefit is accentuated in scan architectures with fewer scan chains, test sets with more don’t care bits, and designs with larger variances of weight differences for transitions in the scan cells.     

cdma2000 1x技术及其发展

文章以cdma20001x为中心,介绍了CDMA标准的发展、与cdma20001x的相关技术、从cdmaOne向cdma20001x演进策略及cdma20001x的发展趋势。     

A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)

This paper presents a new technique for detecting delay faults by observing the fault effects within slack intervals. Delay faults are detected through a comparison of the circuit outputs captured in the scan flip-flops with those from a matched known good neighboring die on the wafer. These outputs are captured in the flip-flops at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. Specially designed test chips were designed and tested to verify the applicability of the methodology. Simulation studies were also conducted to investigate the effectiveness of the technique. The results presented here clearly establish the significant potential of the proposed new delay testing approach     

Delay fault testing using partial multiple scan chains

Delay test patterns can be generated at the functional level of the circuit using a software prototype model, when the primary inputs, the primary outputs and the state variables are available only. Functional delay test can be constructed for scan and non-scan sequential circuits. Functional delay test constructed using software prototype model can detect transition faults at the structural level quite well. Therefore, we propose a new iterative functional test generation approach. The proposed approach involves a partial multiple scan chain construction using the results of functional delay test generation at a high level of abstraction. The iterativeness of the method allows finding the compromise between the test coverage, hardware overhead and test length. Furthermore, using the partial multiple scan chains requires less hardware overhead resulting in shorter test application times. The experimental results are provided for the ITC’99 benchmark circuits. Experiments showed that the obtained transition fault coverage is on average 2% higher than using full scan and commercial automatic test pattern generator for transition faults.     

Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Interposer-based 2.5-dimensional integrated circuit (2.5D IC) is considered as a promising solution to problems like wire delay and power consumption faced by the semiconductor industry today. Since the interconnect wires in the silicon interposer may be defective during fabrication and assembly, they must be adequately tested to ensure product qualification. This paper presents an efficient interconnect test architecture to detect open, short and delay faults, which is compatible with the IEEE 1149.1 standard. It provides a new boundary scan structure with low test power consumption. To reduce the overall test cost, a data-package based test structure is proposed to match the test data transfer volume between TSVs and scan chains. Interconnects of multiple dies can be tested simultaneously under constrains of test power with minimum external test pins. The simulation results validate the effectiveness of the proposed test method. We also present synthesis results to evaluate the area overhead.     

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s _max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s _max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s _max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法

为减少三维芯核绑定前和绑定后的测试时间,降低测试成本,提出了基于跨度和虚拟层的三维芯核测试外壳扫描链优化方法.所提方法首先通过最大化每条测试外壳扫描链的跨度,使得绑定前高层电路和低层电路的测试外壳扫描链数量尽可能相等.然后,在TSVs(Through Silicon Vias)数量的约束下,逐层的将虚拟层中的扫描元素分配到测试外壳扫描链中,以平衡绑定前后各条测试外壳扫描链的长度.实验结果表明,所提方法有效地减少了三维芯核绑定前后测试的总时间和硬件开销.     

Efficient Path Delay Testing Using Scan Justification

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip‐flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS’89 benchmark circuits show that the number of testable paths can be increased by about 45% over the conventional functional justification.     

Core-unified soc test data compression and application

The pattern run-length coding test data compression approach is extended by introducing don’t care bit (x) propagation strategy into it. More than one core test sets for testing core-based System-on-Chip (SoC) are unified into a single one, which is compressed by the extended coding technique. A reconfigurable scan test application mechanism is presented, in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added. The proposed union test technique is applied to an academic SoC embedded by six large ISCAS’89 benchmarks, and to an ITC’ 02 benchmark circuit. Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores, the proposed scheme can not only improve test data compression/decompression, but also reduce the redundant shift and capture cycles during scan testing, de-creasing SoC test application time effectively.     

最高性能处理器TMS320C64x及其在通信中的应用

介绍了美国德州仪器公司最高性能的新一代数字信号处理器TMS320C64x系列的基本特点，对即将推出的C6414，C6415和C6416三种型号数字信号处理器进行了比较，并重点介绍了C64x系列在通信领域的主要应用以及开发C64x系列器件的方法等等。     

全扫描设计中多扫描链的构造

本文在交迭测试体系 的基础上提出了一种多扫描链的区间构造法,对于确定的测试向量集能够显著地减少测试应用时间.该构造方法根据规定的扫描链数,通过求解线性规划问题的方法确定扫描寄存器在扫描链上的优化的分布区间,从而构造多扫描链,最后根据对多扫描链进行连线复杂度的定性分析,求得连线复杂度最低的多扫描链的最优构造.     

Delay Test Generation: A Hardware Perspective

An important problem one faces during design of a built-in self-test(BIST) based delay test is the selection of a proper generator toapply the test vectors. This problem is due to the need of applyinga pair of patterns to detect any given delay fault. The secondvector has to be launched against the logic immediately following thefirst vector. This timing requirement places severe restrictions onthe kind of hardware suitable for the task, especially in built-inself-test applications where the generator must reside on chip.This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. Thedifferent options are measured based on their performance, cost, and flexibility.     

Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture

A two-stage scan architecture is proposed to constrain transition propagation within a small part of scan flip-flops. Most scan flip-flops are deactivated during test application. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-flop in the multiple scan chains drives a group of scan flip-flops in the second stage. Scan flip-flops in different stages use separate clock signals. Test signals assigned to scan flip-flops in the multiple scan chains are applied to the scan flip-flops of the second stage in one clock cycle after the test vector has been applied to the multiple scan chains. There exists no transition at the scan flip-flops in the second stage when a test vector is applied to the multiple scan chains     

Test power reductions through computationally efficient, decoupled scan chain modifications

SOC test time minimization hinges on the attainment of core test parallelism; yet test power constraints hamper this parallelism as excessive power dissipation may damage the SOC being tested. We propose a test power reduction methodology for SOC cores through scan chain modification. By inserting logic gates between scan cells, a given set of test vectors & captured responses is transformed into a new set of inserted stimuli & observed responses that yield fewer scan chain transitions. In identifying the best possible scan chain modification, we pursue a decoupled strategy wherein test data are decomposed into blocks, which are optimized for power in a mutually independent manner. The decoupled handling of test data blocks not only ensures significantly high levels of overall power reduction but it furthermore delivers computational efficiency at the same time. The proposed methodology is applicable to both fully, and partially specified test data; test data analysis in the latter case is performed on the basis of stimuli-directed controllability measures which we introduce. To explore the tradeoff between the test power reduction attained by the proposed methodology & the computational cost, we carry out an analysis that establishes the relationship between block granularity & the number of scan chain modifications. Such an analysis enables the utilization of the proposed methodology in a computationally efficient manner, while delivering solutions that comply with the stringent area & layout constraints in SOC as well.