Band-Structure and Quantum Effects on Hole Transport in p-MOSFETs

Using a Monte Carlo method, we investigate hole transport in ultrasmall p-channel Si MOSFETs with gate lengths of 25 nm. The device simulator couples a 2D Poisson solver with a discretized 6 × 6 k.p Hamiltonian solver that includes the effect of the confining potential and provides the subband structure in the channel region. In addition, carriers in the source and drain regions are treated as quasi 3D particles and the band-structure information is included by solving for the eigenenergies of a more compact 6× 6 k.p Hamiltonian.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

Efficient three‐dimensional parallel simulations of PHEMTs

An efficient 3D semiconductor device simulator is presented for a memory distributed multiprocessor environment using the drift–diffusion (D–D) approach for carrier transport. The current continuity equation and the Poisson equation, required to be solved iteratively in the D–D approach, are discretized using a finite element method (FEM) on an unstructured tetrahedral mesh. Parallel algorithms are employed to speed up the solution. The simulator has been applied to study a pseudomorphic high electron mobility transistor (PHEMT). We have carried out a careful calibration against experimental I–V characteristics of the 120 nm PHEMT achieving an excellent agreement. A simplification of the device buffer, which effectively reduces the mesh size, is investigated in order to speed up the simulations. The 3D device FEM simulator has achieved almost a linear parallel scalability for up to eight processors. Copyright © 2005 John Wiley & Sons, Ltd.     

Numerical simulation on novel FinFETs: asymmetric poly-silicon gate FinFETs and TiN gate FinFETs

We report our numerical study on the device performance of an asymmetric poly-silicon gate FinFET and FinFET with TiN metal gate structure. Our numerical simulation revealed that the asymmetric poly-silicon FinFET structure and TiN gate FinFET structures exhibit superior V _T tolerance over the conventional FinFET structure with respect to the variation of fin thickness. For instance, the V _T tolerance of the asymmetric poly-Si FinFET were 0.02 V while TiN gate FinFET exhibited 0.015 V tolerance for the variation of the fin thickness of 5 nm (from 30 to 35 nm) while the conventional FinFET demonstrates 0.12 V fluctuation for the same variation of the fin thickness. Our numerical simulation further revealed that the threshold voltage (V _T) can be controlled within the range of −0.1∼+0.5 V through varying the doping concentration of the asymmetric poly-silicon gate region from 1.0×10¹⁸ to 1.0×10²⁰ cm⁻³.     

Statistical study of the effect of interface charge fluctuations in HEMTs using a 3D simulator

The intrinsic parameter fluctuations associated with the discreteness of charge and matter become an important factor when the semiconductor devices are scaled to nanometre dimensions. The interface charge in the recess regions of high electron mobility transistors (HEMTs) has a considerable effect on the overall device performance. We have employed a 3D parallel drift-diffusion device simulator to study the impact of interface charge fluctuations on the I-V characteristics of nanometre HEMTs. For this purpose, two devices have been analysed, a 120 nm gate length pseudomorphic HEMT with an In_0.2Ga_0.8As channel and a 50 nm gate length InP HEMT with an In_0.7Ga_0.3As channel.     

Search for Optimum and Scalable COSMOS

We introduce a novel CMOS device architecture capable of building complementary logic operation using only a single gate stack. The new architecture, named complementary orthogonal stacked MOS (COSMOS), places the n and p-MOSFETs perpendicular to one another under a single gate, integrating them vertically as well as laterally. The COSMOS architecture would not only mean significant savings in active device area of a conventional static CMOS pair, but also significant reductions in RC device parasitics. We demonstrate how the device may be built, operated and optimized for symmetric operation, as well as verifying logic NOT operation via 3D device simulations. COSMOS architecture appears to have peculiar scaling trends such as increasing threshold at reduced gate dimensions. The increase in drive voltages lead to faster operation at the expense of higher static leakage and loss of noise margins.     

Computational study of double-gate graphene nano-ribbon transistors

The ballistic performance of graphene nanoribbon (GNR) MOSFETs with different width of armchair GNRs is examined using a real-space quantum simulator based on the Non-equilibrium Green’s Function (NEGF) approach, self-consistently coupled to a 3D Poisson’s equation for electrostatics. GNR MOSFETs show promising device performance, in terms of low subthreshold swing and small drain-induced-barrier-lowing due to their excellent electrostatics and gate control (single monolayer). However, the quantum tunneling effects play an import role in the GNR device performance degradation for wider width GNR MOSFETs due to their reduced bandgap. At 2.2 nm width, the OFF current performance is completely dominated by tunneling currents, making the OFF-state of the device difficult to control.     

Simulations of Sub-100 nm Strained Si MOSFETs with High-κ Gate Stacks

By including soft-optical phonon scattering within an ensemble Monte Carlo simulator, this paper studies the impact of high-κ gate stacks on the performance of n-type Si and strained Si MOSFETs. The simulated devices replicate the performance of sub-100 nm Si and strained Si MOSFETs fabricated by IBM. The results indicate a significant reduction in the device performance due to the presence of a high-κ gate dielectric in both Si and strained Si transistors.     

Quantum Corrected Full-Band Cellular Monte Carlo Simulation of AlGaN/GaN HEMTs

A full-band Cellular Monte Carlo (CMC) approach is applied to the simulation of electron transport in AlGaN/GaN HEMTs with quantum corrections included via the effective potential method. The best fit Gaussian parameters of the effective potential method for different Al contents and gate biases are calculated from the equilibrium electron density. The extracted parameters are used for quantum corrections included in the full-band CMC device simulator. The charge set-back from the interface is clearly observed. However, the overall current of the device is close to the classical solution due to the dominance of polarization charge.     

Simulations of Scaled Sub-100 nm Strained Si/SiGe p-Channel MOSFETs

This paper investigates scaled sub-100 nm strained Si channel p-type MOSFETs. For a 30–40% Ge content SiGe buffer, 1D Poisson-Schrödinger analysis indicates that the parasitic effects of the SiGe buffer are negligible in small devices with high n-type channel doping (>10¹⁷ cm^?3). The device published by IBM and calibrated by us has been scaled down to a 35 nm physical gate length and shows notable performance enhancement over the Si control MOSFET. Well-tempered MOSFET designs have also been adopted to study potential performance improvement associated with the introduction of a strained Si channel. These provide a performance improvement comparable with the scaled versions of the IBM devices for effective gate length down to 25 nm. Improved well engineering is required to suppress short channel effects during the scaling process.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

Analysis of nonequilibrium phenomena on electric characteristics of advanced MOSFETs by using a quantum energy transport model

In this paper, we have investigated nonequilibrium effects for advanced MOSFETs by using a device simulator with quantum energy transport (QET) model. The QET model allows to simulate nonequilibrium carrier transport as well as quantum confinement. The QET model includes the mobility model as a function of carrier temperature in order to consider the nonlocal effects. We have simulated advanced MOSFETs down to 20 nm gate length using the QET model. The QET model is compared with the quantum drift diffusion (QDD) model which includes a mobility model with local assumptions. It is found that the nonlocal mobility model is needed to simulate the advanced MOSFETs with less than 40 nm.     

Frequency Analysis of 3D GaAs MESFET Structures Using Full-Band Particle-Based Simulations

The goal of this contribution is to use a three dimensional (3D) full-band particle-based simulator to investigate 3D scaling effects of static and dynamic current-voltage characteristics of GaAs MESFET structures. The full-band particle-based simulator is also applied to a novel dual-gate GaAs MESFET structure.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Tetrahedral elements in self-consistent parallel 3D Monte Carlo simulations of MOSFETs

Novel thin-body architectures with complex geometry are becoming of large interest because they are expected to deliver the ITRS prescribed on-current when semiconductor transistors are scaled into nanometer dimensions. We report on the development of a 3D parallel Monte Carlo simulator coupled to a finite element solver for the Poisson equation in order to correctly describe the complex domains of advanced FinFET transistors. We study issues such as charge assignment, field calculation, treatment of contacts and parallelisation approach which have to be taken into account when using tetrahedral elements. The applicability of the simulator is demonstrated by modelling a 10 nm gate length double gate MOSFET with a body thickness of 6.1 nm.     

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

Two-dimensional subthreshold current model for dual-material gate SOI nMOSFETs with single halo

A two-dimensional (2D) model for the subthreshold current in the dual-material gate (DMG) silicon-on- insulator (SOI) MOSFET with a single halo is presented. The model considers single halo doping in the channel near the source and a dual-material gate to derive the channel potential using the explicit solution of the 2D Poisson’s equation. Together with the conventional drift-diffusion theory, this results in the development of a subthreshold current model for the novel structure. Model verification is carried out using the 2D device simulator ISE. Excellent agreement is obtained between the calculations and the simulated results of the model. __________ Translated from Chinese Journal of Semiconductors, 2008, 29(4): 746–750 [译自 : 半导体学报]     

Comparison of Double-Gate MOSFETs and FinFETs with Monte Carlo Simulation

A full-band Monte Carlo simulator has been used to analyze and compare the performance of n-channel double-gate MOSFETs and FinFETs. Size quantization effects were accounted for by using a quantum correction based on Schrödinger equation. FinFETs are a variation of typical double-gate devices with the gate surrounding the channel on three sides. From our simulations, we observed that the quantization effects in double-gate devices are less significant as compared to bulk MOSFETs. The total sheet charge density drops only slightly as the depletion of charge at the interface is counterbalanced by the increased volume inversion effect. We also observed an appreciable drop in average velocity distribution when quantum corrections were applied. For FinFETs, the fin extension lengths on either side of the gate affect the device performance significantly. These underlap regions have low carrier concentration and behave as large resistors. The current drops non-linearly with increasing fin extension lengths.     

Can silicon FinFETs satisfy ITRS projections for high performance 10 nm devices?

We utilize a fully self-consistent quantum mechanical simulator based on CBR method to optimize 10 nm FinFET devices to meet ITRS projections for High Performance (HP) logic technology devices. Fin width, gate oxide thickness, and doping profiles are chosen to reflect realistic values. We find that the device on-current approaching the value projected by ITRS for HP devices can be obtained using unstrained conventional (Si) channel. Our simulation results also show that quantum nature of transport in ultra small devices significantly enhances the intrinsic switching speed of the device. In addition, small signal analysis has been performed. Sensitivity of device performance to the process variation at room temperature has also been investigated.     

Global Modeling of high frequency devices

In this work, we utilize the Finite-Difference Time Domain (FDTD) Method coupled to a full-band, Cellular Monte Carlo (CMC) simulator to model the behavior of high-frequency devices. Replacing the quasi-static Poisson solver with a more exact electromagnetic (EM) solver provides a full-wave solution of Maxwell’s equations, resulting in a more accurate model for determining the high-frequency response of microwave transistors.