An adaptive checker for the fully differential analog code

This paper discusses the design of an adaptive checker for concurrent error detection in fully differential analog circuits. The checker monitors the fully differential analog code, which states that, in nominal operation, the common mode signal of any symmetric node pair remains within a narrow band around the quiescent DC bias. The checker measures the common mode voltage and reports an error whenever the measured value exceeds a threshold. Its key feature is that this comparison threshold is dynamically adjusted in order to lower the probability of false alarms. The design was fabricated in a 0.5-/spl mu/m CMOS technology. The chip test results prove the feasibility of the adaptive thresholding concept.     

Precise CMOS current sample/hold circuits using differential clockfeedthrough attenuation techniques

New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-μm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than ±0.4 μA for the input currents from -550 μA to 550 μA. The acquisition time for a 900-μA step transition to 0.1% settling accuracy is 150 ns. For a 410-μA_p-p input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm² and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits     

Measurement of digital noise in mixed-signal integrated circuits

This paper proposes a method of measuring the influence of digital noise on analog circuits using wide-band voltage comparators as noise detectors. Noise amplitude and r.m.s voltage are successfully measured by this method. A test chip is fabricated to measure the digital noise influence. From the experimental results, it is shown that the digital noise influence can be considerably reduced by using a differential configuration in analog circuits for mixed-signal IC's. The digital noise influence can be further reduced by lowering the digital supply voltage. These results show that the voltage-comparator-based measuring method is effective in measuring the influence of digital noise on analog circuits     

Current-mode subthreshold MOS implementation of the Herault-Juttenautoadaptive network

The authors explore translinear circuits in subthreshold MOS technology and current-mode design techniques for the implementation of neuromorphic analog network processing. The architecture, also known as the Herault-Jutten network, performs an independent component analysis and is essentially a continuous-time recursive linear adaptive filter. Analog I/O interface, weight coefficients, and adaptation blocks are all integrated on the chip. A small network with six neurons and 30 synapses was fabricated in a 2-μm double-polysilicon, double-metal n-well CMOS process. Circuit designs at the transistor level yield area-efficient implementations for neurons, synapses, and the adaptation blocks. The authors discuss the design methodology and constraints as well as test results from the fabricated chips     

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology     

Analog Circuit Design Methodology in a Low Power RISC Microprocessor

There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm² test chip with the super H architecture using 0.35-m four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.     

An insect vision-based motion detection chip

The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog processing cell comprises a photodetector, circuits for spatial averaging and multiplicative noise cancellation, differentiation, and thresholding. The operation and configuration of the analog cells is controlled by digital circuits, thus implementing a reconfigurable architecture which facilitates the evaluation of several newly designed analog circuits. The chip has been designed and fabricated in a 1.2-μm CMOS process and occupies an area of 2×2 mm²     

A Design Style for VLSI CMOS

CMOS is an attractive technology for the realization of VLSI systems. However conventional static CMOS design techniques lead to circuits which are slower and much less densely packed than equivalent NMOS circuits. After a brief review of precharge-discharge techniques, a novel method for designing clocked dynamic CMOS is described. This uses a four-phsse clocking scheme that is free from race and charge-sharing problems and results in faster, more compact layouts. A test chip and a full custom 25 000 transistor serial signal processing chip have been designed using this technique. Results obtained by probing the test ship are presented.     

A CMOS 5-V analog front end for 9600-bit/s facsimile modems

A CMOS 9600-b/s facsimile-modem analog front end was designed with the consideration that it be capable of being fabricated on the same chip with digital signal processing circuits. To achieve the dynamic range required in the high-speed QAM (quadrature amplitude modulation) modem environment with a single 5-V power supply, a fully differential architecture is used. The die area is 23 kmil/SUP 2/ and the power consumption is only 35 mW. The experimental results show that 76-dB dynamic range is achieved from the fully differential bandpass filter. The zero crossing detector in the MF-1 detection block can normally operate with -50-dBm input signal.     

A 1.3 GHz SOI CMOS test chip for low-power high-speed pulseprocessing

A test chip has been fabricated in a fully depleted SOI CMOS process with 0.25-μm drawn gate length, It successfully demonstrates the types of circuits required to perform digital filtering, detection, and data thinning functions at high clock speeds. The test chip contains over 5000 transistors and was clocked at speeds up to 1.3 GHz. A target application for these circuits is a very wideband compressive receiver for real-time spectral analysis, which requires digital signal processing to be performed on a 20-Gb/s data stream formed by digitizing a stream of fast analog pulses. Adjustable high-speed on-chip clocks, input and output registers, and large decoupling capacitors allowed testing of the chip to be performed using an inexpensive, low-speed probe card and a standard wafer prober     

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.     

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit design. In this study, we present a fully digital on-chip reliability monitor for high-resolution frequency degradation measurements of digital circuits. The proposed technique measures the beat frequency of two ring oscillators, one stressed and the other unstressed, to achieve 50 X higher delay sensing resolution than that of prior techniques. The differential frequency measurement technique also eliminates the effect of common-mode environmental variation such as temperature drifts between each sampling points. A 265 X 132 mum²test chip implementing this design has been fabricated in a 1.2 V, 130 nm CMOS technology. The measured resolution of the proposed monitoring circuit was 0.02%, as the ring oscillator in this design has a period of 4 ns; this translates to a temporal resolution of 0.8 ps. The 2 mus measurement time was sufficiently short to suppress the unwanted recovery effect from concealing the actual circuit degradation.     

Unified built-in self-test for fully differential analog circuits

The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Analysis of harmonic distortion in single-channel MOS integrated circuits

Presents a general analysis for the calculation of harmonic distortion in single-channel monolithic analog MOS integrated circuits. Power series expressions are obtained for basic stages often used in an analog MOS technology. These include the depletion load inverter, enhancement load inverter, depletion load source follower, enhancement load source follower, and the differential pair. From the power series expressions, the second-order harmonic distortion is calculated. These results are compared with data obtained from a test chip.     

Challenges in analog and mixed-signal fault models

The design and testing of mixed-signal integrated circuits have enjoyed a renaissance in recent years. As is customary with past developments, however, design outpaces testing, and the drive to integrate analog and digital circuits on the same chip exacerbates the test problems. This article reviews the recent results in analog fault modeling-a critical area of mixed-signal testing-and describes the coming challenges for both industrial and university researchers     

An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-/spl mu/m CMOS

This paper presents architecture, circuits, and test results for a single-ended, simultaneously bidirectional interface capable of a total throughput of 8 Gb/s per pin. The interface addresses noise reduction challenges by utilizing a pseudodifferential reference with noise immunity approaching that of a fully differential reference. The transmitter supports on-chip termination, predistortion, and low-skew near-end outgoing signal echo cancellation. The receiver's sense amplifier evaluates the average of two differential input signals without use of analog components and utilizes imbalanced charge injection to compensate for offset voltages. A test chip integrated in a 0.35-/spl mu/m digital CMOS technology uses the proposed techniques to implement an 8-bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gb/s per pin.     

0.5-V analog circuit techniques and their application in OTA and filter design

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.     

A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC

A set of power minimization techniques is proposed for pipelined ADC's. These techniques include commutating feedback-capacitors, sharing of the op-amp between the adjacent stages of the pipeline, reusing the first stage of the op-amp as comparator pre-amp, and exploiting parasitic capacitors for common-mode feedback. This set of low-power design techniques is incorporated in an experimental chip fabricated in a 1.2-μm, double-poly, double-metal CMOS process. At 12-b 5-Msample/s, the chip dissipates 33 mW of power from a 2.5-V analog supply while achieving a maximum differential nonlinearity (DNL) of -0.78 and +0.63 least-significant bits (LSB) with a peak signal-to-noise ratio (SNR) of 67.6 dB