A mechanism of threshold voltage changes for WNx gate GaAs MESFETs in high temperature storage life tests

Reliability of 0.8 μm WN_x gate GaAs MESFETs with a self-aligned lightly doped drain structure has been investigated by means of high temperature storage life tests at 250, 275 and 300 °C. The observed reduction in threshold voltage followed by drain current increase was just reverse in contrast to those for ‘gate sinking’ effect reported on several Au-based gates. The correlation of the threshold voltage reduction with Shottky barrier height and other MESFET parameter changes during the tests suggested a model related to the short channel effect for the threshold voltage reduction, which was proved true by submitting samples of gate lengths 0.7, 1.0 and 1.5 μm to high temperature storage life tests. The dependence of threshold voltage changes on gate orientation relative to the crystal axis was also evaluated with 1.0 μm gate MESFETs to investigate the model in more detail. MESFETs parallel to [001] axis showed minimum absolute threshold voltage changes, while those parallel to piezoelectrically active [011] and [0 1] axes showed decreasing and increasing threshold voltage changes, respectively. From these results, the threshold voltage changes were tentatively ascribed to the relief of the stress caused by poly-imide die bonding process for packaging MESFET chips. In other words, WN_x gate GaAs MESFET chips themselves were concluded to show no appreciable degradation up to 1000 hr storage life tests at 250 and 275 °C, except for ohmic contact degradation at 300 °C.     

Electromigration of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite flip–chip solder bumps with Ti/Ni(V)/Cu under bump metallurgy

We examine electromigration fatigue reliability and morphological patterns of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite solder bumps in a flip–chip package assembly with Ti/Ni(V)/Cu UBM. The flip–chip test vehicle was subjected to test conditions of five combinations of applied electric currents and ambient temperatures, namely, 0.4 A/150 °C, 0.5 A/150 °C, 0.6 A/125 °C, 0.6 A/135 °C, and 0.6 A/150 °C. The electrothermal coupling analysis was employed to investigate the current crowding effect and maximum temperature in the solder bump in order to correlate with the experimental electromigration reliability using the Black’s equation as a reliability model. From available electromigration reliability models, we also present a comparison between fatigue lives of Sn–37Pb solder bumps with Ti/Ni(V)/Cu and those with Al/Ni(V)/Cu UBM under different current stressing conditions.     

The isocurrent test: A promising tool for wafer-level evaluation of the interconnect reliability

A highly accelerated wafer-level electromigration test, the isocurrent test, is presented. A constant high current is used to give both the current and temperature stress to a 4-point resistor with a bonding pad layout which minimizes temperature gradients. The test is used to evaluate unpassivated Al---Cu and passivated Al---Si---Cu lines of different line width. Log normal failure distributions are obtained and the line width dependence of the MTTF and DTTF is similar to that observed in classical electromigration tests. A storage test at 250 °C clearly deteriorates the lifetime of 0.5 and 0.7 μm passivated lines. This is probably due to stress induced void formation.     

Threshold voltage shift in 0.1 μm self-aligned-gate GaAs MESFETs under bias stress and related degradation of ultra-high-speed digital ICs

Bias-temperature stress examinations of self-aligned 0.1 μm length gate GaAs MESFETs have revealed a shift of threshold voltage related to Si doping concentration near the gate sides next to the channel region. With lower doping concentration, the increase in threshold voltage in FETs was faster and a 100 mV increase leads to a 20% reduction of operation speed in digital ICs after forward-biased storage at 200°C. The recovery of the performance under reverse-biased stresses was observed. The degradation is released by increasing Si doping concentration and thus we obtained the prediction of a median life exceeding 10⁶ h at 100°C by setting the Si dose of 4 × 10¹³ cm⁻², which is as high as it can be set without causing serious reduction of breakdown voltage.     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

MOCVD of ferroelectric thin films

A low-pressure chemical vapor deposition system for growing ferroelectric thin PZT films has been developed. It consists of a dispensing and vaporizing system for up to four liquid metal precursors and a cold wall reactor, where the reactions are carried out at pressures below 1 Torr and at temperatures between 330 and 500°C. The thickness of the deposited films ranged from 10 nm to 1 μm. The investigated films in this report are lead-titanate, PbTiO₃, and lead-zirconate-titanate, Pb(Zr,Ti)O₃.     

Dielectric tunable properties of (Ba1−xSrx)TiO3 thin films on LaAlO3 substrate

(Ba_1−xSr_x)TiO₃ (1−x=0.8, 0.7, 0.6 and 0.5) thin films were prepared on (0 0 1) LaAlO₃ substrates by sol–gel method. The films were found to be crystallized in preferential (0 0 1) orientation after post-deposition annealing at 750°C for 1.5 h and 1100°C for 2 h in air, respectively. We investigated the dependence of tunability and dissipation factor on annealing temperature and different Ba/Sr ratios. It was found that the tunability increased dramatically and dissipation factor decreased obviously with increasing annealing temperature, and Ba_0.6Sr_0.4TiO₃ thin films annealed at 1100°C for 2 h have a tunability of 46.9% at 80 kV/cm bias filed and a dissipation factor of 0.008 at 1 MHz.     

Ultra-short pulsed laser deposition and patterning of SiC thin films for MEMS fabrication

A Ti:Sapphire (IR 800-nm) femtosecond (fs) pulsed laser was used to ablate a sputtering grade of silicon carbide (SiC) in an ultra-high vacuum chamber. The laser-induced plasma species were then driven and grown to form 3C-SiC films of about 1 μm thick on single crystal silicon wafers at 20 °C (room temperature) and 500 °C. Scanning electron microscopy, atomic force microscopy, X-ray photoelectron microscopy, X-ray diffraction and nanoindentation were used to characterize the structure, composition, thickness and properties of the SiC films. Results of the femtosecond-pulse laser deposited (fs-PLD) films were compared with those obtained by atmospheric pressure chemical vapor deposition (APCVD) and nanosecond-pulse laser (excimer laser at 248-nm) deposition (ns-PLD). The distinctive features of fs-PLD films are their extremely smooth surfaces, stoichiometry, amorphous structure and low defect density compared to APCVD films, along with better film quality and higher growth rates than ns-PLD films. In addition to film growth studies, a SiC microgripper (to grab 20-μm-sized objects) was micromachined by use of the fs-pulsed laser to demonstrate the utility of ultra-short PLD in SiC-device fabrication.     

New encapsulation development for fine pitch IC devices

The continuous reduction of chip size driven by the market demand has a significant impact on circuit design and assembly process of IC packages. Shrinking chip size and increasing I/O counts require finer bond pad pitch and bond pad size for circuitry layout. As a result, serious wire deflection during transfer molding process could make adjacent wires short, and this issue becomes more critical as a smaller wire diameter has to be applied for the finer pitch wire bonded IC devices.This paper presents a new encapsulation process development for 50 μm fine pitch plastic ball grid array package. Since reduced wire diameter decreases the bending strength of bonded wires significantly, wire deflection during molding process becomes quite serious and critical. Experiments on conventional transfer molding were conducted to evaluate wire span threshold with 23.0 μm diameter gold wire. The results show that the wire span threshold is about 4.1 mm, which is much shorter than the wire span threshold of over 5.0 mm for wire with 25.4 μm diameter. Finite element analysis shows there is a significant difference in the wire deflection between 23.0 μm gold wire and 25.4 μm gold wire diameter under the same action of mold flow. A novel encapsulation method is introduced using non-sweep solution. The wire span could be extended to over 5.0 mm with wire sweep less than 1%. Reliability tests conducted showed that all the units passed 1000 temperature cycles (−55 to 125 °C) with JEDEC moisture sensitivity level 2a (60 °C/60% relative humidity for 120 h) and 3 times reflow (peak temperature at 220–225 °C). It is believed that this solution could efficiently overcome the risk of wire short issues and improve the yield of ultra fine pitch wire bonds in high-volume production.     

Hydrogen incorporation, diffusivity and evolution in bulk ZnO

Hydrogen is readily incorporated into bulk, single-crystal ZnO during exposure to plasmas at moderate (100–300°C) temperatures. Incorporation depths of >25 μm were obtained in 0.5 h at 300°C, producing a diffusivity of 8 × 10⁻¹⁰ cm²/V s at this temperature. The activation energy for diffusion is 0.17 ± 0.12 eV, indicating an interstitial mechanism. Subsequent annealing at 500–600 °C is sufficient to evolve all of the hydrogen out of the ZnO, at least to the sensitivity of Secondary Ion Mass Spectrometry (<5 × 10¹⁵ cm⁻³). The thermal stability of hydrogen retention is slightly greater when the hydrogen is incorporated by direct implantation relative to plasma exposure, due to trapping at residual damage.     

Reliability of industrial packaging for microsystems

Packaging concepts for silicon-based micromachined sensors exposed to harsh environments are explored. By exposing the sensors directly to the media and applying protection at the wafer level the packaging and assembly will be simplified as compared to conventional methods of fabrication.Protective coatings of amorphous silicon carbide and tantalum oxide are suitable candidates with etch rates below 0.1 Å/h in aqueous solutions with pH 11 at temperatures up to 140°C. Si-Ta-N films exhibit etch rates around 1 Å/h. Parylene C coatings did not etch but peeled off after extended exposure times at elevated temperatures. The best diamond-like carbon films we tested did not etch, but delaminated due to local penetration of the etchants.Several glue types were investigated for chip mounting of the sensors. Hard epoxies, such as Epotek H77, on the one hand exhibit high bond strength and least degradation and leakage, but on the other hand introduce large sensor output drift with temperature changes. Softening of the Epo-tek H77 was observed at 70°C.An industrially attractive thin-film anodic silicon-to-silicon wafer bonding process was developed. Glass layers are deposited at 20 nm/s (1.2 μm/min) by electron-beam evaporation and bond strengths in excess of 25 N/mm² are obtained for bonding temperatures higher than 300°C.Through-hole electrical feedthroughs with a minimum line width of 20μm and a density of 250 wires per cm were obtained by applying electro-depositable photo-resist. Hermetically sealed feedthroughs were obtained using glass frits, which withstand pressures of 4000 bar.     

A case study of statistical process control on the prime process using PLASMASK 302U

In this paper, Statistical Process Control (SPC) and statistically designed experiments will be used to optimise a recently developed resist schemes i.e., PRIME (Positive Resist Image by dry Etching). Orthogonal experiments are designed and conducted in order to produce 0.2 μm lines repeatably in PLASMASK 302U resist. Design rules of 0.1 μm are used due to proximity effects. The data is then explored and analysed using surface plots, boxplots, analysis of variance (ANOVA) and linear regression. It was deduced that e-beam dose and 2nd step etch time were the most significant parameters in the process. Linewidth of 0.2 gm and below were achieved with low values of e-beam dose (250–350μC/cm²) and high values of silylation temperature (205–215°C). The optimum range for NUV flood dose was easily found.     

Temperature dependence of snap-back breakdown up to 300°C analyzed using circuit level model and simulation

The MOS snap-back breakdown and its temperature dependence were investigated up to 300°C using silicided LDD-NMOS transistors. The snap-back sustaining voltage increases from 8.25V at room temperature to 8.9V at 300°C (for L_eff=0.56μm). By using extracted parameters for a simple lumped element model we explain this behaviour originating from an increasing avalanche breakdown voltage and slope of avalanche multiplication factor compensating the increase in bipolar gain with temperature.     

Analysis of high temperature effects on performances and hot-carrier degradation in DC/AC stressed 0.35 μm n-MOSFETs

The transistor performances and hot-carrier reliability in n-MOSFETs are investigated at high temperature in the range 25–125 °C. A careful analysis of the temperature dependence of the device parameters shows that transistor performances are significantly reduced and that the Fermi potential, the mobility and current reductions, contribute to decrease the device sensitivity to the hot-carrier damage at high temperature. Different degradation behaviors are found between DC and AC stressing depending on the degradation mechanisms i.e. whether the interface trap generation or oxide charge trapping dominates which consequently exhibits a strong temperature dependence through their magnitude and localization. It is pointed out that the reduction of the ionization rate significantly impacts the degradation behaviors at elevated temperature. Even if the amount of generated damage is slightly larger than what effectively influences the transistor characteristics, the parameter insensitivity to given at high temperature improves the transistor reliability. This improvement is determined in the value of the device lifetime at 125 and 70 °C using inverter and pass transistor operations in a 0.35 μm LDD complementary metal-oxide semiconductor (CMOS) technology suitable for 3.3 V operation.     

Thermal stability of Al/Ni gate AlGaAs/GaAs HEMT's

The study on the instability of gate contacts of Al/Ni gate AlGaAs/GaAs HEMT's was performed by means of storage tests carried out at three different temperatures: 200°C, 240°C and 300°C. Data from tests as long as 5000 hours were analyzed. At the highest temperature the main failure mode was the reaction between the Al of the gate electrode and the Au of the metallization. At 200°C, 240°C an increase of the barrier height was detected. The activation energy determined and the comparison with the data existing in literature is reported.     

The effects of buffer thickness on GaAs MESFET characteristics: channel–substrate current, drain breakdown, and reliability

The effects of thickness in metal–semiconductor field effect transistor (MESFET) GaAs buffer on the device electrical performance and reliability have been investigated. Devices studied are 0.8-μm-gate GaAs MESFETs at different buffer thickness of 0.5 and 0.3 μm from similar MBE-grown processes. Three-terminal off-state breakdown measurements indicate that a substantial enhancement in the observed breakdown current for thinner-buffer MESFETs is attributed to the drain–source leakage or breakdown through the channel–substrate interface while the device is at pinch-off. DC and RF biased stress lifetests up to 323 °C channel temperature have been performed to accelerate the degradation mechanisms. It is found that the device degradation rate has little dependence on buffer thickness when stressed at a reversed gate–drain voltage below 70% of its breakdown threshold. The differences grow rapidly when biased close to the breakdown field because of the development of channel–substrate current in thinner buffer materials.     

Reliability and performance of a true enhancement mode HIGFET for wireless applications

Freescale’s true enhancement mode (EMODE) HIGFET is a high performance single supply technology used for wireless power amplifiers. It is the first technology of its kind to be produced in a high volume manufacturing environment. The EMODE HIGFET intrinsic reliability was evaluated using a conventional three temperature DC accelerated stress test. The device used for these tests has a total gate width of 0.6 mm, a gate length of 0.8 μm, and a die thickness of 3 mils. The device has no through-wafer vias, is representative of the unit cell for larger devices, and was processed using a production mask set.For targeted applications with a system life of 5 years, the first expected failure at 150 °C for the 1 ppm level was determined to be 82 years at a 90% lower confidence level, which exceeds the reliability requirements for subscriber unit power amplifiers by a wide margin. This work demonstrates that EMODE HIGFET devices are high performance RF devices with intrinsic reliability well in excess of anticipated system requirements.     

Rapid thermal magnetic annealing as an emerging technology in field-annealing of thin magnetic films for recording heads

An emerging field where rapid thermal processing (RTP) is now rapidly finding its first acceptance is in the industrial manufacturing of thin-film head devices for magnetic recording. Here soft-magnetic thin-film flux guide structures (usually composed of high-moment alloys containing iron, etc.) are applied onto ceramic substrate wafers (such as Al₂O₃–TiC) of sizes up to 150 mm and subsequently ‘activated' by heating and cooling in a magnetic field.We assessed the advantages of rapid thermal magnetic annealing (RTMA) in a new prototype reactor with an external electromagnet, capable of generating an extremely homogeneous magnetic field of 660 Oe (52.8 kA/m) with field lines parallel across the entire wafer area (150 mm in diameter). Samples with 1 μm thick amorphous iron-alloy layers (Fe₇₇Nb₁₁N₁₀Si₂) sputter-deposited onto ceramic substrates of single-crystalline GGG-garnet (Gd₃Ga₅O₁₂) were conventionally annealed and RTMA-annealed in N₂/H₂ at temperatures between 550 and 700°C. Structural analysis by transmission electron microscopy (TEM) and electron diffraction showed that the enhanced performance of the RTMA-annealed layers is due to the different nanocrystallization kinetics induced by the fast heating and cooling rates of RTMA.The ceramic substrate materials normally used in head manufacturing (such as Al₂O₃–TiC) have favorable grey-body properties with high emissivity (≥0.7) over a wide range of temperatures (25–700°C) and wavelengths (1.5–10 μm), which excludes the difficulties encountered in pyrometric temperature control of infrared-transparent substrates such as silicon. We conclude that RTMA yields superior soft-magnetic materials, where throughput numbers of ≥30 wafers/h are possible.     

a-SiC:H/SiO2 Laminated Polarization Splitter for the Wavelength Region Longer Than 1.3 μm Prepared by Plasma-Enhanced Chemical Vapor Deposition

A laminated polarization splitter for the wavelength region longer than 1.3 μm is fabricated for the first time. It is composed of a-SiC:H/SiO₂ alternative multilayers prepared by plasma-enhanced chemical vapor deposition. Splitting behavior is also verified experimentally. It has low absorption loss even for the wavelength region around λ = 1.3 μm because the band-gap energy of a-Sic is larger than that of a-Si. The measured splitting angle is 13.8°, which is 2.4 times larger than the 5.7° splitting angle of rutile. The absorption loss of the multilayer is reduced to 1 × 10^-3 dB/μm at λ = 1.3 μm. The magnitude of the residual stress is 9.45 × 10⁸ dyn/cm², which is about one-third of that prepared by the rf bias sputtering equipment which is used for another project of our group. The deposition rate of SiO₂, is increased to 135 nm/min, which is 27 times larger than that prepared by the sputtering equipment.     

Dielectric properties of Fe-doped BaxSr1−xTiO3 thin films on polycrystalline substrates at temperatures between −35 and +85 °C

Large-area Ba_xSr_1−xTiO₃ (BSTO-x) thin films, partially Fe-doped, have been grown by pulsed laser deposition (PLD) on technically relevant polycrystalline alumina based ceramics. The capacity (dielectric constant _r) and Q-factor of planar Pt/BTO:Fe/Pt capacitors were investigated within a temperature range from −35 to +85 °C. The applied DC-bias voltages were up to 10 V and the measurement frequency was 1 kHz.Although operating in the ferroelectric state below the Curie temperature, pure BaTiO₃ (BTO) thin films showed the smallest variation of _r within the temperature range from −35 to +85 °C compared to BSTO-0.6 and BSTO-0.8. The temperature dependence of _r below the Curie temperature (ferroelectric state) seems to be smaller than above the Curie temperature (paraelectric state) for the BSTO-x system. A homogeneous tunability of the capacity of about 60% was achieved for applied electrical DC voltages resulting in electrical field strengths between 0 and 5 V/μm within the whole temperature range. The Q-factor of 2 μm thick BTO films increases with increasing DC bias voltage. Furthermore, by Fe-doping of BTO films Q-factors could be increased by a factor of three up to about 70 compared to the not doped films. In addition, the temperature dependence of capacity is considerably influenced by Fe-doping.At a microwave frequency of 30 GHz high _r values of about 1500 were measured for large-area BSTO-0.45 films at room temperature deposited directly on microwave ceramic substrates. Low values of tanδ of about 0.003 were measured for the PLD-BSTO-0.45 films which corresponds to a Q-factor of more than 300. The results show the potential of ferroelectric BTO thin films for applications as tunable electronic devices in a wide temperature range.