一种高效率的适合于低功耗应用的电荷泵电路

设计实现了一种高效率的电荷泵电路。利用电容和晶体管对电荷传输开关进行偏置来消除开关管阈值电压的影响。同时,通过对开关管的的衬底进行动态的偏置使得在电荷传输期间当开关管打开时其阈值电压较低,在开关管关断时其阈值电压较高。该电荷泵电路的效率得到了提高。基于0.18μm,3.3V标准CMOS工艺实现了该电路。在每级电容为0.5pF,时钟频率为780KHz,电源电压为2V的情况下,测得的8级电荷泵的输出电压为9.8V。电荷泵电路和时钟驱动电路从电源处总共消耗了2.9μA的电流。该电荷泵电路适合于低功耗的应用。     

A low noise high efficiency buck DC-DC converter with sigma-delta modulation

Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode(DCM) controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.     

A low power low noise analog front-end for ECG recording

Analog Integrated Circuits and Signal Processing - This work presents a power-efficient and noise-efficient amplifier for ECG recordings. To improve power efficiency, all the transistors in the...     

A multielement high power monopulse feed with low sidelobe and high aperture efficiency

A multielement high power monopulse feed was investigated for excitation of a phased array. This feed has the advantages of high antenna efficiency, effective independent sidelobe control for the sum and difference patterns, and high power handling capability. A 32-element device has been designed which yields theoretical sidelobe levels less than -31 dB for both the sum and difference patterns over the 2800 to 3200 MHz frequency band. The aperture efficiency is 69.5 percent which includes 0.1 dB spillover loss and 1.40 dB tapering loss. The difference slope efficiency defined as the actual slope gain over the maximum possible value is 50 percent at midband. An experimental feed was constructed to verify the predicted performance characteristics. Measured data on both the radiation patterns and the antenna gain agreed very Well with the analytical results. The measured sidelobe level is below -30 dB for all sum and difference beams over the 2800 to 3200 MHz. In addition, this feed can be designed for low power intensity at the feed aperture so that very high power operation can be attained.     

AlInAs/GaInAs on InP HEMTs for low power supply voltage operation of high power-added efficiency microwave amplifiers

High power-added efficiency microwave power amplifier results are reported for AlInAs/GaInAs on InP HEMTs operated at relatively low power supply voltages (2.5-3 V). C-band power amplifiers are reported with power-added efficiencies as high as 67%, and output powers between 200 and 300 mW. This excellent performance at low power supply voltages is attributed to the high gain and low access resistances of the devices, which leads to a high drain efficiency despite the low power supply voltage.<>     

A small, low power boost regulator optimized for energy harvesting applications

A small, low power bootstrapped boost regulator is introduced that can start up with an input voltage of 240 mV and achieve a maximum efficiency of 97 %. The proposed circuit uses two separate control schemes for startup and steady-state operation. A fixed-frequency oscillator is used to initially start up the circuit and raise the output voltage. Once the output voltage has reached a level adequate to bias the internal circuitry, a constant-on-time style hysteretic control scheme is used, which helps increase system efficiency compared to using a conventional pulse-width-modulated control scheme. While maintaining a high efficiency, the proposed circuit only requires three external components: two capacitors (input and output) and an inductor. The effectiveness of this approach is shown through Spectre simulation results.     

A high-frequency, low volume, point-of-load power supply fordistributed power systems

A resonant version of the DC-DC forward converter is presented in which both the primary-side switch and the secondary-side diode are either on or off at the same time. Such a topology is capable of operation in the 10-MHz range, and can be used for very-low volume point-of-load conversion in distributed power systems. This type of converter takes advantage of a very low transformer leakage inductance to achieve zero-voltage switching of all its power semiconductor devices. Its resonant ring is also independent of load current. A 50-W prototype operating at 3.6 MHz is presented along with a discussion of the changes necessary to achieve 10 MHz     

Power Si-MOSFET operating with high efficiency under low supply voltage

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.     

A wideband low power low phase noise dual-modulus prescaler

This paper describes a novel divide-by-32/33 dual-modulus prescaler(DMP).Here,a new combination of DFF has been introduced in the DMP.By means of the cooperation and coordination among three types,DFF, SCL,TPSC,and CMOS static flip-flop,the DMP demonstrates high speed,wideband,and low power consumption with low phase noise.The chip has been fabricated in a 0.18-μm CMOS process of SMIC.The measured results show that the DMP’s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier.The core area of the die without PAD is 57×30μm~2.Due to its excellent performance,the DMP could be applied to a PLL-based frequency synthesizer for many RF systems,especially for multi-standard radio applications.     

一种宽带低功耗低相位噪声的双模预分频器

本文设计了应用SCL、TPSC和CMOS静态三种类型的触发器配合工作的新型双模预分频器。与传统使用单一种类型触发器的双模预分频器相比,该双模预分频器更容易获得高速、宽带、低功耗和低相位噪声的性能。为了验证此设计的性能,采用了SMIC 0.18um CMOS 工艺流片实现。在电源电压为1.8V的条件下测试,此双模预分频器的工作频率范围从0.9 GHz 到 3.4 GHz ;当输入信号为 3.4 GHz时,其功耗为2.51mW,相位噪声为-134.78 dBc/Hz @ 1 MHz. 其核心面积为 is 57um*30um。鉴于其良好的性能,可以应用于许多射频系统的频率综合器中,特别在多标准无线通信系统中。     

A low noise, high resolution silicon temperature sensor

High resolution temperature measurement is essential for determination of blood perfusion in biomaterials. A compact, low noise, high resolution temperature sensor designed for use in an invasive tissue property measurement probe is presented. The circuit is based on traditional proportional-to-absolute-temperature (PTAT) principles. A feedback technique is used to improve linearity and reduce noise. Data from test chips shows temperature resolution of 3 m°C. The chips were fabricated using a 1.75 μm double poly, single metal modified CMOS process designed for this project     

用于便携式健康监护设备的低功耗、低噪声模拟前端电路

本文介绍的用于处理人体生物电信号的模拟前端电路包括仪表放大器、滤波器和可变增益、带宽放大器。仪表放大器采用电容耦合输入来消除直流电极失调。基于电流反馈拓扑结构的IA通过在输入和反馈网络中采用电容分压器来降低功耗。并且,仪表放大器的输入差分对采用互补CMOS输入来提高输入跨导以减小等效输入热噪声。该电路采用Global Foundry 0.35微米 CMOS 工艺流片,电路消耗的总电流为3.96uA,电源电压为3.3V。测试得到的等效输入噪声是0.85uVrms(0.5-100Hz), 噪声能效因子值为6.48。     

用于ZigBee的2.4GHz低功耗双增益低噪声放大器

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

A 2.4-GHz low power dual gain low noise amplifier for ZigBee

e figure (NF) is 2.3-3 dB in the whole 2.45-GHz ISM band. The measured 1-dB compression point, IIP3 and IIP2 is -9, 1 and 33 dBm, respectively. The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

A speed, power, and supply noise evaluation of ECL driver circuits

We present an emitter coupled logic (ECL) active pull-down (APD) circuit which can provide a 10:1 ratio between active and inactive currents. The new APD circuit is compensated for variations in supply and temperature via a clamp voltage. The proposed circuit is evaluated by comparing its performance (in terms of speed, power dissipation, and generated supply noise) with the performance of five other driver circuits     

一种大功率低噪声的智能可调LED驱动设计方法

针对大型LED显示屏驱动中恒流源功率较小、调光不便捷,其开关特性导致的噪声大的问题,提出一种体积小,适用功率大且纹波效果较好的智能优化式恒流LED驱动设计方法。该设计在以往低电流的基础上进行改进,通过运放反馈调节将输出电流的开关特性转换为线性,辅以通断RCD回路(峰值吸收回路)和构建优化式大电流环式PCB布局,能进行光源检测的电流转脉宽式精准调光,输出能够较完善地抑制开关噪声。该设计方法能实现上位机网络远程数字调光,内、外部模拟调光,多路板载级联的智能控制。实验表明:该恒流驱动输出电流可达10A,功率可达370W,输出电流误差小于1%,驱动光源光功率稳定,光照分布均匀,具有较好的纹波效果,稳定可靠。     

Design of a low power voltage regulator for high dynamic range of load current

This paper presents a design technique of a low power, linear voltage regulator for high dynamic range of load current with good transient performances. It has been achieved by introducing a dynamic leakage path (pull down) at the driver stage of the voltage regulator. The pull down current through the dynamic leakage path is kept very small in steady condition for minimizing internal static power. While in high-to-low load current transition, the current through the dynamic leakage path is magnified for a small duration of time to achieve smaller settling time. The concept of the dynamic leakage path proves to be a more power efficient method than the static leakage method, especially in low standby current applications. The circuit is implemented in 0.18?µ CMOS technology and the voltage regulator generates 1.9?V from 3.3?V supply. The dynamic leakage path consumes additional 37?µA current, averaged over 7.2?µS time when the load current switches from high to low value, but consumes only 14?µA current in steady state.     

Concurrent detection of power supply noise

We propose a methodology for the concurrent detection of power supply noise affecting a general synchronous system and exceeding a tolerance bound to be chosen according to the system's constraints. Our solution is based on a suitable self-checking scheme which concurrently monitors a signal of the system clock distribution network and which is, by design, able to provide an output error message upon the occurrence of power supply noise. The produced error indication can then be exploited to recover from the detected noise (thus guaranteeing system's correct operation), or to accomplish diagnosis. Our scheme negligibly impacts system's performance, features self-checking ability with respect to a wide set of possible internal faults and keeps on revealing concurrently the occurrence of power supply noise, despite the possible presence of noise affecting also ground.     

一种分高低压供电的低压差线性稳压器的设计

针对传统低压供电的低压差线性稳压器线性响应比较慢的情况,提出了一种基于BICMOS 0.5μm工艺分高低压供电的低压差线性稳压器。经过Hspice仿真验证,该稳压器具有高增益、高PSRR（Power Supply Rejection Ratio,电源抑制比）、低功耗、响应速度快的特点,输入电压范围为0.5~28.0 V,输出电压为5 V。此稳定器低频时的开环增益达到86 dB,相位裕度为68o,低频时的电源电压抑制比为–91 dB,高频时也能达到–2 dB,静态电流只有13.5μA。