Analog Genetic Encoding for the Evolution of Circuits and Networks

This paper describes a new kind of genetic representation called analog genetic encoding (AGE). The representation is aimed at the evolutionary synthesis and reverse engineering of circuits and networks such as analog electronic circuits, neural networks, and genetic regulatory networks. AGE permits the simultaneous evolution of the topology and sizing of the networks. The establishment of the links between the devices that form the network is based on an implicit definition of the interaction between different parts of the genome. This reduces the amount of information that must be carried by the genome, relatively to a direct encoding of the links. The application of AGE is illustrated with examples of analog electronic circuit and neural network synthesis. The performance of the representation and the quality of the results obtained with AGE are compared with those produced by genetic programming.     

Automated passive filter synthesis using a novel tree representation and genetic programming

This paper proposes a novel tree representation which is suitable for the analysis of RLC (i.e., resistor, inductor, and capacitor) circuits. Genetic programming (GP) based on the tree representation is applied to passive filter synthesis problems. The GP is optimized and then incorporated into an algorithm which can automatically find parsimonious solutions without predetermining the number of the required circuit components. The experimental results show the proposed method is efficient in three aspects. First, the GP-evolved circuits are more parsimonious than those resulting from traditional design methods in many cases. Second, the proposed method is faster than previous work and can effectively generate parsimonious filters of very high order where conventional methods fail. Third, when the component values are restricted to a set of preferred values, the GP method can generate compliant solutions by means of novel circuit topology.     

Controllable decoding for automated analog circuit structure design

The decoding scheme is a major problem in automated analog circuit topology synthesis since decoding schemes bias synthesized circuit structures. However, the proper decoding scheme varies depending on the method to realize a given function. In this paper, a controllable decoding scheme is proposed in which the method to realize a function is controlled by a set of prototype circuits. Thus, the system can generate different types of analog circuits in a unified method. The prototype circuits are designed by a human and suggested to the system as hints of configurations of new analog circuits to be synthesized by the system. In the synthesis process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. A genetic algorithm is then used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are generated with a proposed technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through synthesis examples of a cubing circuit synthesis as a current-mode design and a logic circuit synthesis as a voltage-mode.The authors would like to thank the reviewers for their valuable comments. The authors would like to express special thank to Dr. Andrew M. Abo for English corrections.     

CNTFET Based Fully Differential First Order All Pass Filter

A novel, carbon nanotube field effect transistor (CNTFET) based fully differential first order all pass filter (FDFAPF) circuit configuration is presented. The FDFAPF uses CNTFET based negative transconductors (NTs) and positive transconductors (PTs) in its realization. The proposed circuit topology employs two PTs, two NTs, two resistors and one capacitor. All the passive components of the realized topology are grounded. Active only fully differential first order all pass filter (AO-FDFAPF) topology is also derived from the proposed FDFAPF. The electronic tunability of the AO-FDFAPF is obtained by controlling the employed CNTFET based varactor. A tunabilty of pole frequency in the range of 10.5 to 26 GHz is obtained. Both the circuits are potential candidates for high frequency fully differential analog signal processing applications. As compared to prior state-of-the-art works, both the realized topologies have achieved highest pole frequency and lowest power dissipation. Moreover, they utilize compact circuit structures and suitable for low voltage applications. Moreover, both topologies work equally well in the deep submicron. The proposed filters are analyzed and verified through HPSPICE simulations by utilizing Stanford CNTFET model at 16 nm technology node. It is observed that the proposed circuit simulation outcomes verify the theory.     

Routine high-return human-competitive automated problem-solving by means of genetic programming

Genetic programming is a systematic method for getting computers to automatically solve problems. Genetic programming starts from a high-level statement of what needs to be done and automatically creates a computer program to solve the problem by means of a simulated evolutionary process. The paper demonstrates that genetic programming (1) now routinely delivers high-return human-competitive machine intelligence; (2) is an automated invention machine; (3) can automatically create a general solution to a problem in the form of a parameterized topology and (4) has delivered a progression of qualitatively more substantial results in synchrony with five approximately order-of-magnitude increases in the expenditure of computer time. These points are illustrated by a group of recent results involving the automatic synthesis of the topology and sizing of analog electrical circuits, the automatic synthesis of placement and routing of circuits, and the automatic synthesis of controllers as well as references to work involving the automatic synthesis of antennas, networks of chemical reactions (metabolic pathways), genetic networks, mathematical algorithms, and protein classifiers.     

有源带阻滤波器的综合

级联型有源滤波器的设计技术已经非常成熟,但二阶节电路的综合是尚未解决的难题。根据有源网络综合理论,给出了有源电路新拓扑结构的综合方法。该方法通过给定的电压符号传输函数,使用关联无穷变量来描述被综合电路中节点导纳矩阵和端口导纳矩阵中的零子和任意子,通过导纳矩阵的扩展导出电路的拓扑结构。这种方法可以综合出新的电路结构;给出了二阶有源带阻滤波器新电路的综合实例。仿真和实测结果验证了该方法的正确性。     

A circuit representation technique for automated circuit design

We present a method of automatically generating circuit designs using evolutionary search and a set of circuit constructing primitives arranged in a linear sequence. This representation has the desirable property that virtually all sets of circuit-constructing primitives result in valid circuit graphs. While this representation excludes certain circuit topologies, it is capable of generating a rich set of them including many of the useful topologies seen in hand-designed circuits. Our system allows circuit size (number of devices), circuit topology, and device values to he evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. In all tasks, our system is able to generate circuits that achieve the target specifications. Although the evolved circuits exist as software models, detailed examinations of each suggest that they are electrically well behaved and thus suitable for physical implementation. The modest computational requirements suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation     

Design automation of a lossless multiport network and its application to image filtering

The paper presents expert tools which are elaborated on the basis of synthesis method of lossless nonreciprocal multiport circuits, composed of gyrators and capacitors. The algorithms are written in C++ and the tools compose a user friendly environment for design automation of filters, filter pairs and filter banks. It is possible to design in this environment not only classical structures like Butterworth, Chebyshev, and Cauer (elliptic) filters. The lossless nonreciprocal prototype circuit allows to design more complex filters, including allpass sections necessary to improve filter phase characteristics. However, the most important possibility is to design multiport circuits, especially in the case of not fully determined filter specifications. On each stage of the design process VHDL-AMS is used to describe the circuits. The obtained prototype gyrator-capacitor circuit can be implemented in OTA-C, SC (switched-capacitor) or SI (switched-current) techniques to realize the filter in CMOS technology. In the paper SI technique is used for layout generation of an image filter in order to illustrate the elaborated synthesis algorithms and tools.     

Time-domain analysis methodology for large-scale RLC circuits and its applications

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts: 1) An approach is proposed to delete all intermediate nodes of RL branches. 2) An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3) The Y toπtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground (P/G) networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.     

Exploiting dynamic micro-architecture usage in gate sizing

Modern high performance microprocessors incorporate an abundance of replicated structural components. Many of these components often experience substantially lower utilization while executing a diverse pool of applications. To recover energy efficiency from the lower utilization, system architects resort to dynamic voltage frequency scaling (DVFS). In this paper, we demonstrate that dynamic adaptations using DVFS are markedly energy inefficient than techniques that design circuits ground up for lower performance. We propose a novel microarchitecture aware gate sizing and threshold voltage assignment algorithm to mitigate this current limitation. Our technique is the first of its kind that exploits architectural slack in gate sizing, and leverages on-chip redundancy and slack. We evaluate this circuit-architectural co-optimization framework in a superscalar processor by combining standard cell based gate sizing flows with state-of-the-art architectural simulation. Our results show 17-46% improvement in the datapath energy efficiency over traditional circuit designs incorporating DVFS schemes.     

Efficient numerical CAD technique for RF and microwave amplifiers

The real frequency technique (RFT) is an efficient numerical method to design the matching networks of microwave active circuits. It provides several advantages over most of the usual techniques. By directly including measured scattering and noise parameter data, it does not require any rational functions or circuit models. Moreover, a predetermined matching circuit topology is not necessary. The described method also allows the design of stability-guaranteed broadband circuits when employing potentially unstable transistors. With the Levenberg–Merquardt algorithm, the RFT can be applied to simultaneously optimize transducer power gain, input and output VSWRs, noise figure, and group delay of a multistage microwave active circuit. Applications as different as low-noise amplifier, active filter, or broadband amplifier are possible. © 1998 John Wiley & Sons, Inc. Int J RF and Microwave CAE 8: 131–141, 1998.     

Analysis and identification of speed-independent circuits on an event model

The object of this article is the analysis of asynchronous circuits for speed independence or delay insensitivity. The circuits are specified as a netlist of logic functions describing the components. The analysis is based on a derivation of an event specification of the circuit behavior in a form of a signal graph. Signal graphs can be viewed either as a formalization of timing diagrams, or as a signal interpreted version of marked graphs (a subclass of Petri nets). The main advantage of this method is that a state explosion is avoided. A restoration of an event specification of a circuit also helps to solve the behavior identification problem, i.e., to compare the obtained specification with the desired specification. We illustrate the method by means of some examples.     

Detection of all single and multiple stuck-at faults in combinational digital circuits using index vector testing

A new method for the testing of combinational digital circuits is presented. The method is based on the concept of the ‘index vector’ of a switching function (Gupta 1987), and represents an extension of syndrome testing. A large percentage of syndrome untestable faults are found to be index vector testable. An approach to testing index vector untestable circuits that relies only on the function realized by the circuit and is independent of the circuit topology is presented. The method can be used for the detection of both single and multiple stuck-at faults in a combinational circuit.     

电动汽车功率驱动单元设计

以电动汽车用永磁同步电机为控制对象,介绍了功率驱动单元的设计方法,包括基本结构、功率器件的选取及其驱动电路设计,以及保护电路的结构和参数设计;该方法选用MOSFET作为功率器件,降低了功率驱动单元设计的成本;采用的保护电路设计方法从参数设计入手,并通过电路布局的优化,极大地降低了MOSFET漏极和源极间dudt引发的干扰,提高了功率驱动单元的性能;应用结果表明,采用该方法设计的功率驱动单元性能优良,已成功应用于电动汽车驱动系统中。     

基于RBF网络的模拟电路故障诊断算法

针对BP神经网络在模拟电路故障诊断上存在的收敛速度慢、易陷入局部最小等不足,提出了一种基于多层小波分解和RBF神经网络的模拟电路故障诊断算法。为提高诊断效率,用多层小波分解能有效提取电路故障特征;用RBF网络优良的泛化能力和快速的非线性逼近能力可以较好的解决模拟电路中存在的容差和非线性问题。故障诊断仿真实验表明,在保证较高故障诊断正确率的情况下,RBF网络的训练次数得到了极大地缩小,有效克服了基于BP网络算法存在的上述不足,极大地提高了模拟电路故障诊断的时间效率。     

结合多信号模型与遗传算法的板级电路测点选取方法

针对传统的电路板测点选取方法需要的输入信息多、工作繁琐、效率低及难以得到全局最优解等问题,提出了一种基于多信号模型与遗传算法相结合的优化方法。首先,通过建立板级电路的多信号流系统模型,获取测点与对应板级电路组成单元的相关性矩阵,并对其进行进一步分析,得出测点组合的测试能力参数。在测点选取数量不大于给定值的情况下,选取测试能力参数作为遗传算法的适应度函数并进行优化搜索,以确定测点的优化选取方案。结合Multisim仿真软件进行低通有源滤波电路系统的故障模拟实验,仿真结果表明,基于多信号模型与遗传算法选取的板级电路测点组合对低通有源滤波电路中的绝大部分故障都有良好的检测和隔离能力,取得了良好的效果,同时该方法也适用于多种其他电路。     

Developing a Domain Model for Relay Circuits

In this paper we stepwise develop a domain model for relay circuits as used in railway control systems. First we provide an abstract, property-oriented model of networks consisting of components that can be glued together with connectors. This model is strongly inspired by a network model for railways made by Bj.rner et. al., however our model is more general: the components can be of any kind and can later be re.ned to e.g. railway components or circuit components. Then we show how the abstract network model can be re.ned into an explicit model for relay circuits. The circuit model describes the statics as well as the dynamics of relay circuits, i.e. how a relay circuit can be composed legally from electrical components as well as how the components may change state over time. Finally the circuit model is transformed into an executable model, and we show how a concrete circuit can be de.ned, checked to be legal, and the reaction to an input can be simulated.     

调节缓存器宽度和布线宽度相结合的优化算法

介绍了将调节缓存器宽度和布线宽度相结合的一种减小连线延迟的优化算法—B＆W算法。算法是以Elmore迟延模型为基础的。该算法在GWSA1的算法基础上考虑调节缓存器宽度的作用,因而比单独的调节布线宽度的算法在运算速度上要快的多。例如它在有8000个缓存器和连线段的情况下,CPU时间仅为0．215秒。B＆W算法同时是一种叠代搜索算法,它能够达到最优解。而且算法可以扩展应用到互连树的情况下,这使它的应用更加广泛。