基于前项补偿的电容层析成像数据采集系统

电容层析成像系统极板间的电容值相对于耦合电容相差近两个数量级,如何补偿耦合电容成为微小电容测量的难点之一。以12电极油水两相流电容层析成像系统为研究对象,在分析了电容层析成像系统原理的基础上,设计了电容层析成像数据采集系统,系统采用前项补偿方法完成了微小电容的测量,并根据实际测量过程所涉及的关键性问题进行了分析和讨论,通过实验验证了此方法是实用可行的,较好地解决了微小电容精确测量问题。     

基于前项补偿的电容层析成像数据采集系统

电容层析成像系统极板间的电容值相对于耦合电容相差近两个数量级，如何补偿耦合电容成为微小电容测量的难点之一。以12电极油水两相流电容层析成像系统为研究对象，在分析了电容层析成像系统原理的基础上，设计了电容层析成像数据采集系统，系统采用前项补偿方法完成了微小电容的测量，并根据实际测量过程所涉及的关键性问题进行了分析和讨论，通过实验验证了此方法是实用可行的，较好地解决了微小电容精确测量问题。     

Analysis of on-chip spiral inductors using the distributed capacitance model

In this paper, a distributed capacitance model (DCM) for monolithic spiral inductors is developed to predict the equivalent coupling capacitances C/sub p/ between the two terminals and the equivalent capacitance between the metal track and the substrate C/sub sub/. Therefore, the characteristics of inductors such as the S parameter, the quality factor Q, and the self-resonant frequency f/sub SR/ can be predicted by its series inductance, equivalent capacitances, and series resistance. A large number of inductors have been implemented in 0.25- and 0.35-/spl mu/m CMOS processes to demonstrate the prediction accuracy. For planar and multilayer inductors, DCM can provide a quick and accurate assessment to the design of monolithic spiral inductors.     

Characteristics of Coupled Microstriplines

Semiempirical design equations for the even- and odd-mode characteristics of coupled microstriplines are presented. The characteristics include capacitance, effective dielectric constant, impedance, and losses. The coupled line capacitances are obtained by suitably dividing the total capacitance into parallel plate and fringing capacitances. These capacitances are then used to determine other characteristics. The accuracy of characteristic impedances obtained from these capacitances is better than 3 percent. The sensitivity of the characteristics of coupled microstriplines to the tolerance in parameters is described. It is observed that the effect of tolerances on the coupling constant of a directional coupler increases with the increase in the value of coupling constant. The effects of dispersion and the finite thickness of metal strips have been included. It is noticed that the dispersion is more pronounced for even mode, whereas finite strip thickness affects odd mode to larger extent.     

Methodology for characterization of high-speed multi-conductor metal interconnections and evaluation of measurement errors

Analysis and design of interconnects in high speed integrated circuits and systems involves models in the form of multiconductor transmission lines. The fundamental parameters of those models are matrices of capacitance, (C), inductance, (L), resistance, (R), and conductance (G). We present a methodology for measurement of entries in capacitance matrix. The entries of capacitance matrices can be calculated using numerical solvers of electrostatic fields established under the assumption of suitable biasing of interconnect structures. Numerical calculations of complete field equations are very complex and expensive in terms of computer time, therefore several approximations are made in constructing interconnect dedicated software packages available on the market. Because of these approximations it is necessary to validate the calculations via measurements. Calculation of the off-diagonal entries of capacitance matrix from measurements of "two-terminal" capacitances is strongly corrupted by the measuring errors. The method involves direct capacitance measurement in multi-conductor structures and provides analysis of accuracy.     

Measurements and extractions of parasitic capacitances in ULSI layouts

This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts. It is well known that, in integrated circuits, the signal delay due to interconnects is comparable to that of gates. This aspect becomes particularly important, for example, during the design of clock trees in high-speed applications. In general, capacitance extraction is carried out with software tools but they should be validated on a set of geometrical structures, which have been accurately characterized and that are representative of the circuit layouts. Experimental characterization of these structures and their set up in a golden set of measures is still a challenging task. In this paper, we first describe some experimental approaches to measure capacitances of structures from the golden set and in particular we identify a high accuracy transducer based on pass-gate transistors. We then propose a software implementation of the floating random walk algorithm that solves the drawbacks in the extraction of capacitances of interconnects in a nonhomogeneous medium as an industrial layout. Finally, experimental and simulation results are presented, validating the adopted approach.     

Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution

We present a new test structure measuring inter- and intralayer coupling capacitance parasitic to the same target interconnection with subfemtofarad resolution. The coupling capacitance as well as fringing capacitance measured by the test structure are demonstrated for two-level copper interconnections used in 90-nm technology node. In addition, we demonstrate that the accuracy of layout parameters extraction is improved by nondestructive inverse modeling of a copper interconnect cross-sectional structure, which reproduces the pitch dependence of the measured inter- and intralayer coupling capacitance within about a 1% error.     

DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances

Chemical-mechanical polishing (CMP), active and via fills have become indispensable aspects of semiconductor manufacturing. CMP fills are used to reduce metal thickness variations due to chemical-mechanical polishing. Via fills are used to improve neighboring via printability and reliability of low-k and ultra low-k dielectrics. Active region fills are used for STI CMP uniformity and stress optimization. Although modern parasitic extraction tools accurately handle grounded fills and regular interconnects, such tools use only rough approximations to assess the capacitance impact of floating fills, such as assuming that floating fills are grounded or that each fill is merged with neighboring ones. To reduce such inaccuracies, we provide a design of experiments (DOE) which complements what is possible with existing extraction tools. Through the proposed DOE set, a design or mask house can generate normalized fill tables to correct for the inaccuracies of existing extraction tools when floating fills are present. Golden interconnect capacitance values can be updated using these normalized fill tables. Our proposed DOE enables extensive analyses of fill impacts on coupling capacitances. We show through 3-D field solver simulations that the assumptions used in extractors result in significant inaccuracies. We present analyses of fill impacts for an example technology and also provide analyses using the normalized fill tables to be used in the extraction flow for three different standard fill algorithms. We also extend our analyses and methodology to via fills and active region fills, which have more recently been introduced into semiconductor design-manufacturing methodologies and for which sufficient understanding is still lacking.     

Improving the accuracy and efficiency of junction capacitance characterization: strategies for probing configuration and data set size

In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy.     

A Closed-Form Equation for Estimating Capacitance of Signal Vias in Arbitrarily Multilayered PCBs

This paper provides a significant improvement to the coaxial-line equation that is used for analytical estimation of via capacitance in multilayered printed circuit boards (PCBs) Previously, a pure coaxial-line equation is used for estimating via capacitance with a maximized and minimized number of pads in high-density multilayered PCBs. Now, in the via capacitance equation, both the capacitances associated to via body and via pads in multilayered PCBs with arbitrary stackups are included. Laboratory measurements by a vector network analyzer and digital inductance–capacitance–resistance (LCR) meter, as well as quasi-static and full-wave computational simulations, confirm solid accuracy of the derived equation used for estimating the capacitance of arbitrary signal via geometry common in practice.      

Investigation of interconnect capacitance characterization usingcharge-based capacitance measurement (CBCM) technique andthree-dimensional simulation

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure     

Parasitic capacitance removal of sub-100 nm p-MOSFETs using capacitance–voltage measurements

Capacitance–voltage measurements are performed on sub-100 nm high-k/metal gate p-MOSFETs to extract the intrinsic capacitance per gate length. This is then repeated on simulated devices using finite element modeling to compare to the experimental results. The intrinsic channel capacitance for the simulated devices is isolated from the parasitic capacitance, allowing for the comparison of analytic models of parasitic capacitances to the simulation.     

Comb Capacitor Structures for On-Chip Physical Uncloneable Function

Planar inter-digitated comb capacitor structures are an excellent tool for on-chip capacitance measurement and evaluation of properties of coating layers with varying composition. These comb structures are easily fabricated in a single step in the last metallization layer of a standard IC process. Capacitive coupling of these structures with a coating layer is modelled based on the electric field distribution to have a detailed understanding of contributing capacitance components. The coating composition is optimized to provide maximum spread in capacitance values of comb capacitor structures. This spread in measured capacitance values can be used to implement a physical uncloneable function (PUF). A PUF is a random function which can be evaluated only with the help of a physical system. We present an on-chip capacitive PUF for chip security and data storage in which the unlock key algorithm is generated from capacitors which are physically linked to the chip in an inseparable way. The strength of this key increases with the spread in capacitance values and measurement accuracy.      

基于边界元法的二维VLSI版图电容提取

提出了一种用边界元法计算ＶＬＳＩ版图电容的方法，通过求解二维拉普拉斯方程，直接得到版图中各种类型的电容的值。该方法提取数据准确简单，占用内存少，计算效率高，且有较高的精度。用该方法对几种典型的ＶＬＳＩ版图电容进行提取，均取得较好的结果。     

VLSI circuit reconstruction from mask topology

This paper discusses whether and how parasitic circuit elements must be included in the circuit simulator source file to obtain reliable simulation results. In particular, attention is paid to fabrication tolerances, wire capacitance (including fringing effects), wire resistance (dispersive line effects), coupling capacitances and capacitances associated with contacts and the aspect ratio of (non-rectangular) transistors.     

Coupled Rectangular Bars Between Parallel Plates

Curves are presented giving the even-mode fringing capacitance, the odd-mode fringing capacitance, and the difference between odd- and even-mode fringing capacitances for wide ranges of thickness and spacing of rectangular bars centered between parallel plates. Simple formulas are given relating these capacitances to even- and odd-mode characteristic impedances of coupled rectangular bars. possible applications to strip-line and other circuits are described. The appendix gives the derivation of the fringing, capacitances by conformal mapping techniques. The results are exact for bars extending in width infinitely far from the coupling region, and have only small error (less than 1.24 per cent) for bars whose width is greater than about 35 per cent of the difference between plate spacing and bar thickness.     

The lumped-charge power MOSFET model, including parameterextraction

A fundamentally new, physically-based power MOSFET model features continuous and accurate curves for all three interelectrode capacitances. The model equations are derived from the charge stored on two internal nodes and the three external terminals. A straightforward parameter extraction technique uses the standard gate-charge plot or process data and is matched with interelectrode capacitance measurements. Simulations are in excellent agreement with measurements. The model is used to design a snubber for a flyback converter     

Measurement method for accurate extraction of the base-to-emitterintrinsic and peripheral capacitances of bipolar transistors

A simple measurement method to determine the intrinsic and peripheral emitter junction capacitances is described. The method is based on measurements of BJT's with different emitter geometries and is demonstrated on transistors of an advanced BiCMOS technology. The method can be applied directly to standard deep-submicrometer devices. No special test devices are required. By determining peripheral capacitance for different processes, the method enables the examination of process schemes designed to suppress the effect of the peripheral emitter on the transistor action. The method also provides a useful approach to monitor the scaling behavior of the intrinsic and peripheral capacitances. Results indicate the peripheral capacitance starts dominating the total capacitance as the emitter is scaled into the submicrometer range. For devices with quarter micron emitter widths, the peripheral capacitance is found to be 3 to 4 times higher than the intrinsic capacitance, and puts a fundamental limitation on device design     

Simple determination of all capacitances for a set of parallelmicrostrip lines

A fast and moderately accurate method to describe the complicated dependence on design and process parameters of coupling capacitances between a set of parallel lines is presented in this paper. It involves only one circuit-dependent parameter at a time. This is accomplished by calculating the capacitance coefficient matrix through inversion of a potential coefficient matrix with much simpler dependence on geometry. Self elements are approximately independent of the presence of other lines, and mutual elements do not depend on linewidths or interfering lines as long as the ground is sufficiently far away. The potential coefficients are derived by inverting one- or two-line capacitance matrices that are either theoretically calculated or determined by measurements on integrated circuit (IC) test structures. Look-up tables for a specific IC process can then be constructed with only linewidth as the parameter for self potential elements and distance between line centers as parameter for mutual potential elements. General algorithms have been derived for microstrip on one or two layers of dielectric