A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each other's phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39% PAE (using 1.85-V supply). The active die area is 1.2 mm/sup 2/.     

A three-dimensional CMOS design methodology

A technology-updatable design methodology for three-dimensional (3-D) CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: 1) technology level, 2) mask level, 3) transistor level, and 4) logic level. A novel transistor level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples is presented.     

A three-dimensional CMOS design methodology

A technology-updatable design methodology for three-dimensional CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: (1) technology level, (2) mask level, (3) transistor level, and (4) logic level. A novel transistor-level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples are presented.     

A circuit-level methodology for leakage power reduction of high-efficient compressors in 22-nm CMOS technology

Analog Integrated Circuits and Signal Processing - A new circuit-level methodology called input controlled leakage restrainer transistor (ICLRT) compatible with single threshold CMOS technology is...     

A methodology for projecting SiO2 thick gate oxide reliability on trench power MOSFETs and its application on MOSFETs VGS rating

In this work, a methodology based on the E-model for the reliability projection of a thick (> 20 nm) SiO₂ gate oxide on a vertical trench power MOSFET, is presented. Experimental results suggest that a Logic Level (LL) trench MOSFET with 35 nm of gate oxide can be rated at V_GS = + 12 V if one assumes continuous DC Gate-Source bias of V_GS = + 12 V at T = 175 °C for 10 years at a defect level of 1 Part Per Million (PPM). We will demonstrate that if we take into account MOSFET device lifetime as dictated by the Automotive Electronics Council (AEC Q101) mission profile, then devices can be rated higher to V_GS = + 14.7 V at T = 175 °C for the same PPM level (1 PPM). The application of the methodology for establishing the oxide thickness, t_ox, for any required voltage rating, is discussed.     

A unified design methodology for CMOS tapered buffers

In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are presented for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability of tapered buffers and a two-component physical area model. Each performance criterion is individually investigated and analyzed with respect to the number of stages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. The creation of process dependent look-up tables for optimal buffer design is described, and a methodology to apply these look-up tables to application-specific tapered buffers for both unconstrained and constrained systems is developed     

Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

ESD protection methodology for deep-sub-micron CMOS

Electrostatic discharge is considered to be a serious treat of integrated CMOS circuits since the feature size reached about 1.5-1.0μm. Since then the scaling of CMOS technologies led to an increase of their ESD susceptibility based on geometrical, physical and technological limitations. The paper describes the change in methodology in order to assure a reasonably high target value of ESD protection with newly to be developed deep sub-micron feature size technologies. The backward adaptive conservative methodology is step by step replaced by a methodology considering the ESD issue already during process development and involving more predictive ESD-TCAD into the development cycle. It is concluded that the scaling based limitations might grow to a significant problem in the near future requiring significant effort to assure a reasonable ESD protection level for CMOS technologies, in particular if the high-frequency properties of such technologies should not be affected.     

A high-performance CMOS power amplifier

A high-performance CMOS power amplifier consisting of a new input stager especially suited to power amplifier applications and a variation on a class AB output stage is presented. The amplifier has been fabricated using a conventional silicon gate p-well process. The configuration results in several performance improvements over previously reported high-output current amplifiers without requiring process enhancements. Design details and experimental results are described.     

A coplanar CMOS power switch

A 300 V power switch in a high-voltage CMOS technology compatible with a low-voltage MOS/bipolar technology is presented. This circuit can switch positive and negative 150 V pulses with rise and fall times of 100 ns for a 200 pF capacitive load. The switch has a low-voltage input control (/spl plusmn/15 V). Using earth-symmetrical non-overlapping high-voltage pulses as dynamic supply voltages, it is possible to reduce the power dissipation during the switching time considerably in comparison with the power dissipation of power switches, which use static (i.e., constant) supply voltages under the same conditions.     

Interconnect limits on gigascale integration (GSI) in the 21stcentury

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node     

Design methodology for full custom CMOS microcomputers

A highly structured design methodology is necessary to be successful in the design of VLSI integrated circuits with more than 100000 transistors on a chip. Such a methodology is described: it is based on the regularity of the circuit architecture with an associated chip floor plan and on a new layout technique named metal oriented layout.This methodology has been tested with the design of a 13500 MOS microcomputer. From the instruction set and through different levels of instruction interpretation, the architecture and associated chip floor plan are generated. The detailed logic design is made directly in symbolic layout with the chip floor plan in mind.The proposed design methodology can be best appreciated by the short development time and small chip area required for the designed 13500 MOS microcomputer.     

A methodology for deep sub-0.25 μm CMOS technology prediction

We present a novel methodology for characterization of sub-quartermicron CMOS technologies. It involves process calibration, device calibration employing two-dimensional device simulation and automated Technology Computer Aided Design (TCAD) optimization and, finally, transient mixed-mode device/circuit simulation. The proposed methodology was tested on 0.25 μm technology and applied to 0.13 μm technology in order to estimate ring oscillator speed. The simulation results show an excellent agreement with available experimental data     

Design of CMOS tapered buffer for minimum power-delay product

The tapered buffer is analyzed from the viewpoint of power dissipation. Both uniform and nonuniform tapered buffers are considered. It is found that there is an optimum value of tapering factor for a minimum power-delay product. In case of uniform tapering, we can obtain an analytical solution of the optimum tapering factor for a minimum power-delay product, which is about 1.5~2 times larger than that for a minimum propagation delay. It is also found that there exists a nonuniform tapering factor which gives a global optimum condition for a minimum power-delay product, which, however, results in a larger short-circuit current. Compared with a uniform buffer, a nonuniform tapered buffer shows about 8% improvement in dynamic switching energy, and 3~5% improvement in total switching energy. We confirm this by simulating tapered buffers with SPICE     

Design optimization methodology for deep-submicrometer CMOS deviceat low-temperature operation

The design optimization for 0.3-μm channel CMOS technology at liquid-nitrogen temperature (77 K) is described. The tradeoff between circuit performance and reliability for deep-submicrometer CMOS devices at low-temperature operation is theoretically and experimentally examined. A simulator, which selects power-supply voltage and process/device parameters for low-temperature operation, has been developed. Based upon the simulated results, design optimization for low-temperature operation has been proposed to determine power-supply voltage and various process and device parameters. The optimized design has been demonstrated on a 0.3-μm CMOS device, by utilizing electron beam (EB) lithography· Excellent device characteristics and a functional ring oscillator circuit have been obtained at 77 K     

Biasing technique via bulk terminal for minimum supply CMOS amplifiers

A biasing technique for minimum supply CMOS amplifiers is proposed. The bulk terminals of the input transistors of a pseudo-differential amplifier are exploited in a switched-capacitor control loop to set the quiescent current. Simulations on a design powered with 0.7 V show that the performance obtained is comparable to that of a traditional differential pair supplied with 1 V.     

一种应用于PWM D类音频功率放大器的CMOS Rail-to-Rail比较器

提出了一种应用于CMOS D类音频功率放大器的Rail-to-Rail PWM比较器,其输入级为Rail-to-Rail结构,输出级为AB类输出。基于CSMC 0.5μm CMOS工艺的BSIM3V3 Spice模型,采用Hspice对PWM比较器的特性进行了仿真,典型模型下的直流开环增益为50dB,电源抑制比为52dB,ICMR为0.04V~4.98V,传输时延为24.5ns,版图有效面积为210×75μm2。由于PWM比较器的良好性能参数,所以其不仅适用于D类音频功率放大器,也能应用于各类低频数据转换电路。     

A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers

A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-/spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications.     

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.     

A low power consumption CMOS differential-ring VCO for a wireless sensor

This paper describes a new three-stage voltage controlled ring oscillator (VCO) based on 0.35???m standard CMOS technology. The VCO was designed for a transmitter operating in the 863?C870?MHz European band for wireless sensor applications. The transmitter is designed for binary frequency-shift keying (BFSK) modulation, communicating a maximum data rate of 20?kb/s. In addition to the VCO, the transmitter combines a BFSK modulator, an up conversion mixer, a power amplifier and an 863?C870?MHz band pass filter. The modulator uses the frequency hopping spread spectrum and it is intended for short range wireless applications, such as wireless sensor networks. The oscillation frequency of the VCO is controlled by a voltage V_CTRL. Simulation results of the fully differential VCO with positive feedback show that the estimated power consumption, at desired oscillation frequency and under a supply voltage of 3.3?V, is only 7.48?mW. The proposed VCO exhibits a phase noise lower than ?126?dBc/Hz at 10?MHz offset frequency.