普通运放和MOS管搭建高压源精确测量击穿电压和漏电流

在中小功率半导体器件的参数测试中,不乏一些高压的器件,如何准确稳定地测出这类器件的击穿电压和漏电流是此类仪器最关键的问题之一.解决办法之一是要有个精度高且可程控的电压源作为测试基准源,而市场上输出电压达千伏级的运放器价格昂贵,且购买困难.本文通过普通运算放大器和MOS管构成可程控0～1000V高压运算放大器,并介绍其电路在半导体综合参数测试仪中的应用.     

基于传统的CMOS工艺延伸漏极NMOS功率管研究

延伸漏极N型MOS（EDNMOS）是基于传统低成本CMOS工艺设计制造,用N-well作为NMOS漏极漂移区,以提高其击穿电压。用二维器件模拟软件Medicici对该器件进行模拟分析,结果表明有效地提高了NMOS管击穿电压。实验结果表明采用这种结构能使低压CMOS工艺输出功率管耐压提高到电源电压的2．5倍,样管在5V栅压下输出的电流可达到750mA。作为开关管工作,对于1000pF容性负载,其工作电流在550mA时,工作频率可达500KHz。     

使用MOSFET管不同参数影响研究

总结MOSFET管分类及特点及MOSFET管的温度对开启电压,导通电阻,漏源极电压,漏电流,雪崩能量等参数的影响。     

集成电路测试系统的加流测压及加压测流设计

在集成电路的测试中,通常需要给所测试的集成电路提供稳定的电压或电流,以作测试信号,同时还要对信号进行测量,这就需要用到电压电流源;测试系统能作为测试设备的电压电流源,实现加压测流和加流测压功能。且具有箝位功能,防止负载电压或电流过大而损坏系统。应用结果表明,该检测系统运行稳定可靠,测量精度高。     

应力记忆工艺优化对NMOS器件性能的改善

应力记忆工艺(SMT)通过在NMOS器件沟道中产生张应力,提高器件的电子迁移率,从而提升NMOS器件的性能。Si₃N₄层应力值、SiO₂层厚度以及退火顺序等三种因素,均对NMOS器件的性能产生影响,增加了SMT工艺应用的难度。对三组实验结果进行分析,研究了三种因素对NMOS器件性能的影响,优化了工艺条件。结果表明,NMOS器件应用SMT工艺后,饱和漏极电流-关态漏极电流(I_dsat-I_off)较传统NMOS器件提高了6%。     

自动测试设备加流测压及加压测流的设计

在集成电路的测试中,通常需要给测试的集成电路提稳定的电压或电流,以作测试信号,同时还要对信号进行测量,这就需要用到电压电流源;本系统能作为测试设备的电压电流源,实现加压测流和加流测压功能.本系统具有箝位功能,防止负载电压或电流过大而损坏系统.应用结果表明,该检测系统运行稳定可靠,测重精度高.     

一种抑制关态漏电流和提高亮度稳定性的OLED微显示像素电路研究

OLED微显示像素驱动电路中,由于较小的存储电容和开关MOS管关态漏电流的影响,导致其存储电压和亮度不稳定.通过分析影响关态漏电流的主要因素,提出了一种多开关管串联和存储电容拆分相结合的办法以减小关态漏电流,并设计了一种含有两个开关管和两个存储电容的像素电路,该电路将关态漏电流由大于3 pA减小为0.4pA,存储电压和亮度稳定性得到了很大的改善,小亮度时一帧的亮度变化仅为0.18 cd/m2.电路可实现的最小OLED驱动电流为25 pA,像素亮度范围为1.82～217.37 cd/m2.     

英飞凌30V车用MOSFET具备全球最低通态电阻

英飞凌科技股份公司近日面向大电流应用的汽车推出一款具备全球最低通态电阻的30V功率MOSFET（金属氧化物半导体场效应晶体管）。全新的OptiMOS—T230V MOSFET是一款N沟道器件,在10V栅源电压条件下,漏极电流为180A,而通态电阻仅为0．9毫欧。     

一种高精度曲率补偿带隙基准电压源设计

根据带隙基准电压源的原理,基于CSMC 0.5μm工艺设计了一种高精度二阶曲率补偿带隙基准电压源。利用MOS管工作在亚阈值区时漏电流和栅极电压的指数关系,在高温段对温度特性曲线进行补偿。通过Spectre仿真,得到输出基准电压为2.5 V的电压基准源。工作电压范围为3.35⁷.94 V,1 kHz时电源抑制比为-71.73 dB,温度从-257.94 V,1 kHz时电源抑制比为-71.73 dB,温度从-25¹25℃之间变化时温度系数为7.003×10-6℃-1。     

一种低压高频CMOS电流乘法器的设计

提出了一种新颖的高频四象限电流乘法器电路，该乘法器使用了工作在三极管区的互补MOS器件，并且采用了饱和区MOS管的平方律特性。该电路采用0．35pmCMOS工艺，使用HSpice软件仿真。仿真结果显示，该乘法器电路在±1.18V的电源电压下工作时，静态功耗为1．18mW，-3dB带宽可达到1．741GHz。与先前的电流乘法器电路相比，工作电压降低了，带宽提高了。     

智能汽车系统的电源设计

对任何一个智能控制系统,电源永远都是一个核心的部分。电源能否给系统提供一个稳定充足的电压和电流参量,是评价一个电源优良与否的标准。而智能汽车控制系统对电源具有特殊的要求。针对该系统电源特殊要求进行相关的电源系统设计及其相关元件的取舍,以便系统能很好地运行。     

Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

利用导通电压降监测SLD的输出光功率

由于传统的光功率采集仪精度不高,在实验中无法明显地显示出光功率在短期内的变化,而采集电压的数据采集系统可以很好地解决这个问题。在分析1310 nm超辐射发光二极管(Super Luminescent Diode,SLD)光源的工作原理的基础上,设计了一种在恒温条件下控制驱动电流来使SLD稳定工作的驱动电路,进行了理论分析和实验验证,给出了利用SLD电压降监测输出光功率的新方法,取得了真实可靠的实验数据。通过SLD光源的驱动实验得出输出光功率与驱动电流和SLD两端电压降的相关关系,结果表明,输出光功率与电流具有良好的线性关系,与电压具有良好的正相关指数关系。利用采集电压降监测SLD的输出光功率,大大提高了测试精度和数据分辨率,同时为SLD退化寿命试验提供了新的电学参数。     

ESD laboratory simulations and signature analysis of a CMOS programmable logic product

It is well established in the semiconductor I/C industry that the proportion of customer field returns attributed to damage resulting from electrical over-stress (EOS) and electro-static discharge (ESD) can amount to 40% to 50% (Cook C, Daniel S. Characteristics and failure analysis of advanced CMOS submicron ESD protection structures. EOS/ESD symposium proceedings ?14, Dallas, TX, 1992. p. 147; Denson WK, Green TJ. A review of EOS/ESD field failures in military equipment. EOS/ESO symposium proceedings-10, 1988. p. 7. Straub RJ. Automotive Electronics IC Reliability. CICC Proceedings, 1990; Euzent BL, Maloney TJ, Donner II R. Reducing field failure rate within proven EOS/ESO design. EOS/ESO Symposium Proceedings ?13, Los Vegas, NV, 1991. p. 59). ESD events are the subset of EOS events caused by high voltages that are associated with electrostatic charge. Although additional hard and soft failures can occur in the factory, these are normally screened by effective test programs. It is therefore necessary to determine the probable cause of failure before cost effective corrective action can be initiated.Distinguishing between EOS and ESD failures and differentiating the subtle differences between damage due to the several distinct ESD models continues to challenge failure analysis capabilities as dimensions shrink and critical defect sizes are reduced. Many of the damage sites are not visible with optical microscopy. De-processing together with very high magnification examination using the scanning electron microscope (SEM) is most often necessary. However, the use of test model simulators to replicate the ESD events can most often replicate a failure signature, i.e. a unique die location and morphology associated with the specific model (Morgan IH. ESO Failure Analysis Signatures. Proceedings of the 3rd ESO Forum, Grain, Germany, 1993. p. 275).This paper summarizes the evaluation performed on a standard programmable logic complimentary metal-oxide silican (CMOS) product to ascertain the ESD immunity. The study entailed ESD simulation using a variety of ESD models, conducting detailed physical failure analysis and then comparing the results with documented analyses performed on customer field returns and factory failures. As a result of the differences in current stress magnitude and over-stress time domain, the location, type and severity of damage at the failure site is known to show considerable variation (Morgan IH. A Handbook of ESO models. AMD Internal Publication, 1992 (available from AMD literature department upon request)). The purpose of the study was to develop a catalogue of failure signatures, and to determine to what extent this catalogue could be used to relate a signature to electrical failure for a particular die and pin function.     

30 GHz SiGe active inductor with voltage controlled Q

An active inductor (AI) based on a cascade gyrator for 30 GHz applications implemented with a 0.25 μm in SiGe technology is presented. The gyrator converts not only a key capacitor into an inductor, but also an added resistor, into a negative resistor. This gyrator-RC has its losses compensated by the negative resistor improving the active inductor Q factor. Changing the bias voltage and current allows to obtain a variable AI. A study of a cascade gyrator AI topology is done to understand the circuit behavior and key elements. For this purpose, an AI impedance model is introduced and discussed. An improved AI with the added resistor replaced by a voltage controlled mosfet resistor is proposed. This extra control voltage allows the variable AI quality factor fine tuning. Schematic and circuit extracted from layout simulations are presented, and compared with the measured results of two prototypes of the AIs (one with a fixed resistor and other with a voltage controlled resistor). A prototype of a high pass filter using the AI with fine Q control was fabricated. Non-linear simulations for different input signal levels were performed and compared with measurements. Also discussion on the non-linear models accuracy is performed.     

An efficient method for plasma-charging damage measurement

The initial slope of the voltage versus time curve during constant current stressing of gate-oxide has been demonstrated, for the first time, as a good indicator for plasma-charging damage. This method of damage measurement measures the charge trapping rate of the gate-oxide directly while it is under a high-field stress. It combines the stressing and measuring steps in one rapid measurement. Using only capacitors as testing vehicle, this method does not require extensive processing. Using current stressing instead of CV measurement, this method greatly reduces the measurement time and the size requirement of the capacitor. The ability of this measurement method in bringing out the passivated defects after annealing is demonstrated. An example of using this method in detecting plasma-charging damage is included     

针压敏感芯片圆片测试探索

圆片测试中存在大电流的测试项目,比如基准电压的测试,它会受接触电阻的影响,接触电阻太大会抬高测试回路中模拟地的零点,导致测试的基准电压比真实值偏大。类似于以上描述对于在圆片测试过程中受针压大小影响较大的芯片即为针压敏感芯片;此类芯片在测试过程中一般都需要将探针针压加大或者在测试过程中不断地清针和磨针来减小接触电阻,从而减小测试误差。不断地清针和磨针将会给探针造成不可挽回的损耗,缩短探针的使用寿命。为解决以上问题,介绍了一种解决针压影响测试电压的方法。     

Transient-induced latch-up test setup for wafer-level and package-level

Latch-up triggered by an impulse of short duration, is one root cause for field failures of CMOS devices. Standard tests, like JEDEC 78, which apply quasi-static overvoltage and overcurrent may fail to identify this susceptibility. The presented test method and setup allows to study the transient induced latch-up (TLU) phenomenon employing nstrigger impulses at wafer-level and package-level. A TLU-module superimposes the DC voltage of the power supply with a short stress pulse and delivers the combination to the tested pin of the DUT, avoiding destructive EOS. Closest possible distances between the TLU-module and the DUT and the use of RF-probes at wafer level allow risetimes of less than 1 ns, time resolved measurements of voltage and current, and an almost instantaneous limitation of the supply current after latch-up has been triggered. The short stress pulses were generated by transmission lines or solid state pulse generators. Abrupt changes in the voltage and current amplitudes indicate that latch-up has been triggered. The method is successfully demonstrated for several devices in different technologies.     

Resistive switching characteristic of electrolyte-oxide-semiconductor structures

The resistive switching characteristic of SiO₂ thin film in electrolyte-oxide-semiconductor (EOS) structures under certain bias voltage is reported. To analyze the mechanism of the resistive switching characteristic, a batch of EOS structures were fabricated under various conditions and their electrical properties were measured with a set of three-electrode systems. A theoretical model based on the formation and rupture of conductive filaments in the oxide layer is proposed to reveal the mechanism of the resistive switching characteristic, followed by an experimental investigation of Auger electron spectroscopy (AES) and secondary ion mass spectroscopy (SIMS) to verify the proposed theoretical model. It is found that different threshold voltage, reverse leakage current and slope value features of the switching I-V characteristic can be observed in different EOS structures with different electrolyte solutions as well as different SiO₂ layers made by different fabrication processes or in different thicknesses. With a simple fabrication process and significant resistive switching characteristic, the EOS structures show great potential for chemical/biochemical applications.     

天线效应对LPNP管输出曲线的影响

天线结构是监控半导体工艺过程中等离子体损伤的一种典型结构,一般主要用来监控MOS器件栅氧的损伤。文中,该结构用来监控横向PNP(LPNP)管工艺过程中的发射极结损伤。实验发现,带天线结构的LPNP管的输出曲线容易出现翘曲现象,分析认为该异常不是由于发射极结损伤造成的,因为发射极结工艺过程中并没有受到损伤。同时发现该翘曲现象在LPNP管保护环接低电位时会消失,该低电位在很大范围内变化时,输出曲线基本一致,且输出曲线电流较保护环悬空时的电流整体偏大,在集电极电压较大时,输出电流和保护环悬空时的电流一致。