Threshold-voltage instability in MOSFET's due to channel hot-hole emission

Hydrogen introduced and trapped in the gate oxide of MOSFET's by the silicon-nitride capping process can be activated by emitted holes from the MOSFET channel to produce a large threshold-voltage shift. This effect requires avalanche multiplication in the channel for the production of holes when a dc voltage is applied to the gate. For the pulsed-gate case, the magnitude of the threshold-voltage shift depends significantly on the gate-pulse fall time, cycle time, and duty cycle. In both cases the electric field normal to the Si/SiO2interface near the drain aids the emission of holes across that interface. A semiquantitative model is proposed which says that holes can recombine at H2molecules and release sufficient energy to cause dissociation. The atomic hydrogen created can participate in electrochemical reactions at the gate oxide/channel interface which create nonuniform distributions of trapped charge and interface states along the channel. Model calculations of the time, temperature, and voltage dependences of this threshold instability agree well with measured results.     

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.     

Threshold voltage shift of n-channel Si-gate MOSFET's

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 Å into a p-type silicon substrate of the acceptor concentration of 7 × 10¹⁴/cm³. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10^-12V.cm²below a dose of 5 × 10¹¹ions/cm². Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10^-12V.cm²due to the maximum surface depletion layer.     

Simulating single-event burnout of n-channel power MOSFET's

Single-event burnout of power MOSFETs is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFETs     

Comparison of drain structures in n-channel MOSFET's

Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.     

A study of photon emission from n-channel MOSFET's

It is known that an n-channel MOSFET, operating in the saturation region, is accompanied by visible light emission. The spectral distribution of this emitted light is reported in this paper for the first time. It behaves as exp (-α . hv) under various bias conditions (α: constant); the energy state of hot electrons is described as a Maxwell-Boltzmann distribution. The hot-electron temperature in an n-channel MOSFET is experimentally evaluated from the photon spectrum analysis. As compared with the electric field strength calculated by two-dimensional simulation, the hot-electron temperature is found to be determined as a function of the electric field strength in the drain avalanche region.     

Threshold-voltage analysis of short- and narrow-channel MOSFET's by three-dimensional computer simulation

In small size MOSFET's, short- and narrow-channel effects simultaneously occur. There is a mutual dependency between these effects when the source-to-substrate bias increases or the channel stopper impurity dose under the field oxide surrounding the active region becomes dominant. A three-dimensional numerical program, based on the finite difference method, has been developed to analyze the threshold-voltage changes due to the small size effect. A sufficient convergence rate with acceptable memory size is obtained from optimum node discretization and an initial solution guess with sophisticated boundary conditions. The simulation results are compared with experimental data obtained from actual devices. Good agreement has been obtained on the threshold-voltage change with the channel width, taking into account an accurate QSSprofile. Some numerical and graphical outputs of the device simulator explain the mechanism of small size effects.     

Fabrication of inversion-type n-channel MOSFET's using cubic-SiC on Si

Inversion-type n-channel MOSFET's of cubic-SiC were successfully fabricated. Cubic-SiC was grown on Si     

Dual-gate operation and volume inversion in n-channel SOI MOSFET's

The effects of volume inversion in thin-film short-channel SOI MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two-dimensional device simulations and one-dimensional analytical computations. The analyses have been restricted to the strong inversion regime, which is the practically useful region of operation of the SOI MOSFETs. In this region, the analyses suggest that when compared at constant V _G-V_T values, the dual-channel volume inverted devices do not offer significant current-enhancement advantage, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1-μm range     

Velocity saturation effects in n-channel deep-depletion SOS/MOSFET's

We use the n-channel deep-depletion SOS/MOSFET to measure carrier velocity of electrons in thin SOS films. The data are presented as a function of electric field up to the point where the velocity saturates. We show the consistency of these data across devices of different gate lengths and manufacture operating at different gate voltages. These results lead to the concept of a "universal curve" for the carrier velocity versus electric field relationship which can be applied to the modeling of velocity-saturation effects in n-channel SOS/MOSFET's. We develop a technique for such an application. In addition, by compensating for the effect of surface scattering on mobility, we have been able to show that the velocity versus field relationship at the surface of thin SOS films agrees very closely to that obtained from bulk silicon.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

An analytical model for snapback in n-channel SOI MOSFET's

An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3-μm epi film     

Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's

Fully depleted SOI MOSFET's include an inherent parasitic lateral bipolar structure with a floating base. We present here the first complete physically based explanation of the bipolar gain mechanism, and its dependence on bias and technological parameters. A simple, one-dimensional physical model, with no fitting parameters, is constructed, and is shown to agree well with simulations and measurements performed on a new type of SOI MOSFET structure. It is shown that parameters which affect the gain, such as SOI layer thickness, body doping concentration and gate and drain voltages, do so primarily by affecting the concentration of holes in the body region. Thus, current gain falls dramatically with increasing drain voltage due to the associated impact ionization driven increase in the hole concentration. Gummel plots of this parasitic bipolar indicate an apparent ideality factor of 0.5 for the hole current, due to the body hole concentration's dependence on drain voltage     

Behavior of holes generated by impact ionization in n-channel MOSFET's

The behavior of holes, which are generated mainly by impact ionization, is described with the results obtained from a two-dimensional numerical analysis. The hole density has been found to be large even near the source for shorter channel lengths.     

Thermal effects in n-channel enhancement MOSFET's operated at cryogenic temperatures

Thermal effects in n-channel enhancement-mode MOSFET's operated at cryogenic temperatures are discussed. Device heating is identified as the cause of drain current transients and the origin of this phenomenon is considered. Experimental results are presented in which thermal effects are studied as functions of temperature for various gate and drain biases. Drain current is found to be a monitor of device temperature, From an understanding of the thermal behavior of devices, the channel electron mobility can be examined as a function of temperature and gate bias. The observed thermal effects are explained in terms of material and device properties. The implications for future low-temperature CMOS VLSI development are discussed.     

Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient.     

Relationship between hot-electrons/Holes and degradation of p- and n-channel MOSFET's

The relationship between hot electrons and holes and the degradation of p- and n-channel MOSFET's is clarified by experimentally determining where along the channel the SiO2is most affected by each type of carrier. Transconductance degradation is found to be caused by hot-hole injection in pMOSFET's, and by hot-electron injection in nMOSFET's.     

Influence of post-stress effects on the dynamic hot-carrierdegradation behavior of passivated n-channel MOSFET's

An apparently non-quasi-static degradation behavior is found for nMOS transistors that are dynamically stressed with conditions which favor hot-hole injection. This effect can be ascribed to a post-stress effect occurring during the waiting time between the different pulses. It is shown that this effect is of importance only when a net positive charge is built up during the stress. The deviating behavior under dynamic stress conditions can be predicted based on the measurement of the post-stress effect after a static degradation