Hot-carrier-induced degradation in p-MOSFETs under AC stress

Lifetimes under AC stress are calculated with a quasistatic model using parameters extracted from DC stress data. For inverter-like waveforms, the measurement data show reasonable agreement with the simulation results. For waveforms with turnoff transient occurring in the presence of high drain voltage, more degradation than the model predicts is found if the transient is short (⩽10 ns) and gate voltage is high     

Hot carrier-induced SOI MOSFET degradation under AC stressconditions

The hot-carrier-induced device degradation in partially depleted silicon-on-insulator (SOI) devices has been investigated under AC stress conditions. The device degradation of both floating-body SOI devices and body contacted SOI devices have been measured and analyzed for different AC stress frequencies and gate bias voltages. Possible degradation mechanisms are suggested     

Hot-carrier-induced alterations of MOSFET capacitances: aquantitative monitor for electrical degradation

In this paper, combined gate-to-channel (C_GSD) and gate-to-bulk (C_GB) capacitance measurements are used in order to extract quantitative information about hot-carrier degradation in MOS transistors. An analytical model, explaining the results of accelerated degradation experiments, is presented to establish a simple relationship between C_GSD and C_GB changes and the stress-induced charges Q_ox and Q_it trapped in the oxide or in interface states, respectively. A method, validated by means of two-dimensional (2-D) numerical simulations, is proposed to determine Q_ox and Q_it directly from the measured capacitances, and is applied to experimental data. The new technique considerably improves the capabilities of previous capacitive methods because it can yield a quantitative determination of Q_ox and Q_it     

Hot-carrier-induced degradation in reoxidized-nitrided-oxiden-MOSFETs under mixed AC-DC stressing

Reduced degradation rate can be observed for reoxidized-nitrided-oxide (RNO) n-MOSFETs under dynamic stressing versus the corresponding static stressing. A new degradation mechanism is proposed in which trapped holes in gate oxide are neutralized by the hot-electron injection, with no significant generation of interface states because of the hardening on the Si-SiO₂ interface by nitridation/reoxidation steps. The RNO device degradation during AC stressing arises mainly from the charge trapping in the gate oxide rather than the generation of interface states. Moreover, the AC-stressed RNO devices are significantly inferior to the fresh RNO devices in terms of DC stressing, possibly due to lots of neutral electron traps in the gate oxide resulting from the AC stressing     

The base current degradation of poly-emitter BJTs under AC stress

A simple model for the analysis of the ac stress effect in poly-emitter bipolar transistors is presented. Apart from the reverse-bias induced hot-carrier effects, the forward-bias recovery effect is a key factor under ac stress, it obviously suppresses the base current degradation of the device which is caused during the reverse-bias periods. In this work, we derived the relationship between the excess base current and the stress time for different ac stress conditions. This model is verified with experimental results.<>     

Hot-carrier-induced degradation in p-channel LDD MOSFET's

When the p-channel MOSFET is stressed near the maximum substrate current Isub, the lifetime t (5-percent increase in the transconductance) followstI_{sub} = A(I_{sub}/I_{d})^{-n}, with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratioI_{sub}/I_{d}and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.     

Hot-carrier-induced degradation in nitrided oxide MOSFETs

Hot-carrier-induced degradation in commercially prepared silicon-gate MOSFETs incorporating ammonia annealed, nitrided oxides as the gate dielectric is examined and compared with the degradation observed in similar devices incorporating conventional oxides. Nitridation at 1100°C for 2 h is observed to reduce the rate of transconductance degradation and threshold voltage increase by nearly half, compared to the oxide for stressing at both low and high gate bias, and to modify the effects of stressing on the substrate current characteristics. In contrast, nitridation at 1150°C produces both improvements and degradations in device stability depending on the parameter examined and the stress conditions. While ammonia annealing introduces nitrogen, it also appears to incorporate excess hydrogen in the dielectrics that alters charge trapping and interface-state generation so that the performance of the dielectric under electrical stress depends on the concentrations of both species     

Hot-carrier-induced degradation of LDD polysilicon TFTs

In order to improve the stability of polysilicon thin-film transistors (TFTs) several drain junction architectures have been proposed. In this paper, the hot-carrier (HC) related stability of the lightly doped drain (LDD) TFT architecture is analyzed by using an iterative algorithm that relates the HC induced damage to the carrier injection across the device interfaces with gate and substrate oxide. The resulting creation of interface states and trapped charge is taken into account by using a system of rate equations that implements mathematically the Lais two step model, in which the generation of interface states is attributed to the trapping of hot-holes by centres into the oxide followed by the recombination with hot electrons. The rate equations are solved self-consistently with the aid of a device simulation program. By successive iterations, the time evolution of the interface state density and positive trapped charge distribution has been reconstructed, and the electrical characteristics calculated with this model are in good agreement with experimental data. This algorithm represent an improvement of an already proposed degradation model, in which the interface states formation dynamics is accounted by using a phenomenological approach. The present model has been applied to reproduce the degradation pattern of LDD TFTs and it is found that generation of interface states proceed almost symmetrically on the front and back device interfaces, starting from the points in which the transverse electric field peaks, and moving toward the drain side of the device. The final interface states distribution determines a sort of "bottleneck" in the active layer carrier density, that can explain the sensitivity to HC induced damage of both transfer and output characteristics.     

Hot-carrier-induced degradation of gate dielectrics grown innitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N₂ O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g_m had a 15×improvement over control oxides not grown in a N₂O atmosphere. Further improvement in g_m degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO₂ interface, leading to lower interface state generation (ISG). Improvements were also observed in I_g-V_g characteristics, indicating a reduction of trap sites both at the Si/SiO₂ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N₂O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N ₂O oxides and is a subject for further study     

阶梯栅氧结构的NLDMOS热载流子效应研究

本文对一种新型的阶梯栅氧结构的NLDMOS（Step Gate Oxide NLDMOS , SG-NLDMOS）的热载流子效应进行了研究。采用直流电压应力实验、TCAD仿真、电荷泵测试等方法,对退化现象进行了分析,并提出了退化机制。然后研究了漂移区注入剂量对器件热载流子效应的影响,结果表明低的漂移区注入剂量可以更有效地减小器件导通电阻的退化。     

MOSFET parameter degradation after Fowler–Nordheim injection stress

We have investigated the degradation of tunnel oxides due to Fowler–Nordheim electron injection from polysilicon gate. Tested devices are n-MOSFET normally used for Flash EPROM applications with four different technologies for the tunnel oxide layer. Stresses have been performed at different source and drain bias conditions for a total injected charge up to 1 C/cm². The oxide characteristics and degradation have been determined comparing the MOSFET threshold voltage and transconductance peak for as received devices and after each stress step.     

Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs

The charge-pumping measurement technique was successfully applied to submicron (L_eff = 0.35 μm) n-MOSFETs on ultra-thin (50 nm) SOI film. The hot-carrier-induced degradation is studied by examining the damages to both gate-oxide and buried-oxide (BOX) interfaces. We found that when stressed at maximum substrate current, interface-trap generation is still the primary cause for hot-carrier-induced degradation. Even for ultra-thin-film SOI devices, the hot-carrier-induced damage is locally confined to the gate-oxide interface and only minor damage is observed at the buried-oxide interface. The buried-oxide interface charging contributes less than 5% of the overall drain current degradation.     

Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS(SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment,a TCAD simulation and a charge pumping test.For different stress conditions,degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented.Then the effect of various doses of n-type drain drift(NDD) region implant on R_(on) degradation is investigated.Experimental results show that a lower NDD dosage can redu...     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

Hot-carrier-induced degradation of the back interface inshort-channel silicon-on-insulator MOSFETS

The tolerance of silicon-on-insulator MOSFETs to hot-carrier injection into the buried oxide is investigated. It is shown that stressing of the back channel results in reversible electron trapping and formation of localized defects at the buried interface. This damage is responsible for the transconductance overshoot, large threshold voltage shift, and attenuated kink effect. It is also noticed that even in moderately thin films the back oxide damage does not affect the front-channel operation and, conversely, stressing the front channel does not generate defects at the buried interface. These findings indicate that the hot-carrier degradation of the buried oxide might be chosen as a sensitive criterion for optimizing SIMOX (separation by implantation of oxygen) structures     

Gate oxide degradation of SiC MOSFET under short-circuit aging tests

SiC MOSFETs reliability issues remain a challenge that requires further investigation. In this article, a short-circuit aging test was developed to characterize the electrical parameter evolution. The threshold voltage and gate drain capacitance seem to be relevant degradation indicators. These two parameters indicate a gate oxide degradation. Electron trapping in the oxide layer could be the mechanism behind this deterioration.     

A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress

Enhanced device degradation of low-temperature n-channel polycrystalline thin-film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater severity of degradation. Moreover, a lightly doped drain (LDD) TFT is less strongly affected, and the effect is dominated by accumulated drain-avalanche hot-carrier (DAHC) stress. It was also found that differences between the electric field in the respective channel regions are responsible for the different degradation properties of SD and LDD TFTs. It was shown that the severe degradation under ac stress in an SD TFT is caused by increased DAHC stress, to which electrons emitted from the trap states when the TFT is turned off make significant contributions.     

Hot-carrier-induced degradation of N2O-oxynitrided gateoxide NMOSFETs

Measurement of long term electrical characteristics of N₂ O-oxynitrided gate oxide NMOSFETs revealed that the role of the nitrogen-rich layer as a blocking barrier for molecular hydrogen diffusion is dominant in the reduced device degradation. A two-step model was proposed, in which the release of hydrogen species and their reaction with the trivalent silicon atoms are the main factors for hot-carrier-induced-degradation. Hot carrier immunity of the NMOSFETs was also found to originate partially from the small increase of both the effective barrier height for electron injection and the interface trap creation energy due to the negatively charged nitrogen-rich layer     

Tunnel oxide degradation under pulsed stress

A key issue for Flash cell scaling down is the reduction of tunnel oxide thickness limited by the higher gate leakage current (Stress Induced Leakage Current, SILC) after cycling. It is possible to reduce the oxide degradation during cycling by reducing the stress pulse duration and increase the time between pulses. This allows the annealing of precursor sites with an overall reduction of stable traps. Aim of this work is the investigation of the SILC induced by pulsed stress and the corresponding charge trapped in the oxide during stress. The impact of the oxidation technology will also be discussed.     

Hot-electron-induced MOSFET degradation at low temperatures

The n-channel LDD MOSFET lifetime is observed to followtau=(A/I_{d})(I_{sub}/I_{d})^{-n}from 77 to 295 K when the device is stressed near the maximum Isub. Here Idis the drain current andAis the proportionality constant. The experimental result indicates thatnis approximately 2.7 and is independent of temperature. However, the proportionality constantAfollowsA = A_{0} exp (-E_{a}/kT), withE_{a} = 39meV. The smaller proportionality constant at low temperatures suggests that hot-electron injection (HEI) degradation is caused by the electron trapping in the oxide.