PDSOI 静态随机存储器的总剂量辐照加固

对PDSOI CMOS 器件及电路进行总剂量辐照的加固势必会引起其性能下降,这就需要在器件及电路加固和其性能之间进行折中.从工艺集成的角度,对PDSOI CMOS器件和电路的总剂量辐照敏感区域:正栅氧化层、场区氧化层及埋氧层提出了折中的方法.采用此种方法研制了抗总剂量辐照PDSOI SRAM ,进行总剂量为2×105 rad(Si)的辐照后SRAM的各项功能测试均通过,静态电流的变化满足设计要求,取数时间:辐照前为26.3 ns;辐照后仅为26.7 ns.     

辐照加固SRAM型FPGA总剂量辐射效应研究

在航天辐射环境中,电离辐射产生的辐射效应会对电子元器件性能产生影响。文章对自主研发的SRAM型FPGA芯片在60Co-γ源辐照下的总剂量辐射效应进行了研究。实验表明:(1)总剂量累积到一定程度后功耗电流线性增大,但只要功耗电流在极限范围内,FPGA仍能正常工作;(2)SRAM型FPGA在配置过程中需要瞬间大电流,故辐照后不能立即配置;(3)总剂量辐照实验时,功耗电流能直观反映器件随总剂量的变化关系,可作为判断器件失效的一个敏感参数。该研究为FPGA的设计提供了基础。     

抗辐射128kb PDSOI静态随机存储器

介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×1011 rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验.     

IC’s radiation effects modeling and estimation

The approach for IC's radiation hardness estimation and fault prediction is presented in this paper. It is based on the implementation of low-energy laboratory simulation sources (laser, X-ray, etc.). The possibility of radiation simulator application is based on similarity of physical processes in semiconductor structures causing IC upsets and failures under the radiation environment and under simulation sources. The analysis of adequacy is performed for total dose effects, single event effects, displacement effects and transient radiation effects. The application of imitators permits to change the expensive and low-productive radiation test installations with much more effective simulation sources, based on the dominant effects equivalence. The designed simulation test methods are proved to be an effective tool to different IC radiation hardness estimation and fault prediction in radiation environment.     

Radiation effects in GaAs FET devices

The effects that space and nuclear radiation have on GaAs devices utilized for integrated circuit design are reviewed. The hardness capability of contemporary GaAs devices and logic circuits is presented in terms of four major nuclear and space radiation threat categories: total dose effects, dose rate effects, single particle phenomena, and neutron effects. The experimental test data and theoretical analyses presented demonstrate the tolerance of GaAs discrete JFETs and MESFETs and planar integrated circuits to fast neutron and ionizing radiation, under both transient and cumulative conditions.<>     

The radiation test based assessment of process quality and reliability for conventional 65-nm CMOS technology

This work presents a solution for radiation hardness assessment using compact and productive X-ray facilities, as well as the automated measurement system. The radiation test procedure can be integrated in commercial IC's process as a mandatory option for providing high reliability and radiation hardened IC projects.Using the radiation test procedure as a one of technology stage, the assessment of total ionizing dose (TID) hardness was done for test structures, which were fabricated in conventional 65 nm CMOS technology.     

浮栅ROM与SRAM的辐射效应比较分析

比较了浮栅ROM和SRAM的中子、质子和γ辐射效应的异同,分析了其不同的原因.与SRAM相比,浮栅ROM器件出错时的14MeV中子注量阈值高5个量级;31.9MeV质子注量阈值高4个量级;总剂量损伤阈值相差不大,都在10⁴rad(Si)量级左右.这些都是由二者存储单元的结构和辐射效应机制决定的.在空间辐射环境中,不需经常擦写数据的情况下,应该选用浮栅ROM器件.     

北京正负电子对撞机次级束质子单粒子翻转计算和试验研究

北京正负电子对撞机(BEPC)电子直线加速器试验束打靶产生的次级束中包含质子,其中能量约为50MeV~100MeV的质子占有很大比例,这弥补了国内高能质子源的空白。本工作计算得到次级束中的质子能谱,建立质子单粒子翻转截面计算方法,在北京正负电子对撞机次级束质子辐射环境中,计算静态随机存取存储器的质子单粒子翻转截面,设计了SRAM质子单粒子翻转截面测试试验,发现SRAM单粒子翻转和注量有良好的线性,这是SRAM发生单粒子翻转的证据。统计得到不同特征尺寸下SRAM单粒子翻转截面,试验数据与计算结果相符,计算和试验结果表明随着器件特征尺寸的减小器件位单粒子翻转截面减小,但器件容量的增大,翻转截面依然增大,BEPC次级束中的质子束可以开展中高能质子单粒子效应测试。     

65nm SRAM传统静态指标的测试方案及研究

65 nm及其以下工艺,工艺波动对SRAM性能影响越来越大.SRAM读写噪声容限能够反映SRAM性能的好坏,对于预测SRAM良率有着重要的作用.采用一种新型测试结构测量SRAM读写噪声容限(即SRAM传统静态指标),该测试结构能够测量65 nm SRAM在保持、读、写三种操作下的指标:Hold SNM,RSNM,N-c...     

总剂量辐照加固的PDSOI CMOS 64k静态随机存储器

在国内首次使得1.2μm部分耗尽SOI 64k静态随机存储器的抗总剂量能力达到了1×106 rad(Si),其使用了SIMOX晶圆. 在-55～125℃范围内,该存储器的数据读取时间几乎不变.在经过剂量为1×106 rad(Si)的总剂量辐照后,该存储器的数据读取时间也几乎不变,静态功耗仅从辐照前的0.65μA变化为辐照后的0.8mA,远远低于规定的10mA指标;动态功耗仅从辐照前的33mA变化为辐照后的38.1mA,远远低于规定的100mA指标.     

The effect of γ-ray irradiation on the SOT magnetic films and Hall devices

Magnetoresistive random access memories(MRAMs)have drawn the attention of radiation researchers due to their po-tential high radiation tolerance.In particular,spin-orbit torque MRAM(SOT-MRAM)has the best performance on endurance and access speed,which is considered to be one of the candidates to replace SRAM for space application.However,little atten-tion has been given to the γ-ray irradiation effect on the SOT-MRAM device yet.Here,we report the Co-60 irradiation results for both SOT(spin-orbit torque)magnetic films and SOT-Hall devices with the same stacks.The properties of magnetic films are not affected by radiation even with an accumulated dose up to 300 krad(Si)while the magnetoelectronic properties of SOT-Hall devices exhibit a reversible change behavior during the radiation.We propose a non-equilibrium anomalous Hall effect mod-el to understand the phenomenon.Achieved results and proposed analysis in this work can be used for the material and struc-ture design of memory cell in radiation-hardened SOT-MRAM.     

Design and implementation of a programming circuit in radiation-hardened FPGA

We present a novel programming circuit used in our radiation-hardened field programmable gate array （FPGA） chip.This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back.The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain.It not only saves area but also provides more flexible configuration operations.By configuring the proposed partial configuration control register,our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented.The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well.Also,the radiation hardened by design programming point is introduced.This circuit has been implemented in a static random access memory（SRAM）-based FPGA fabricated by a 0.5μm partial-depletion silicon-on-insulator CMOS process.The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back.Moreover,the radiation test results indicate that the programming circuit has total dose tolerance of 1×10⁵ rad（Si）,dose rate survivability of 1.5×10¹¹ rad（Si）/s and neutron fluence immunity of 1×10¹⁴ n/cm².     

TFT-LCD驱动控制芯片内置SRAM的自测试设计

针对单片集成TFT-LCD驱动控制芯片内置SRAM的特点,提出了一种将内建自测试与机台测试相结合的SRAM测试方案.测试向量由机台提供,测试过程中启动内部自测试电路.在SRAM的读出寄存器和写入寄存器之间建立一条通路,测试向量通过这条通路在SRAM单元之间传递,形成了一个长的移位链,读出数据送给比较器检测.与传统自测试结构相比,该方案面积开销小,灵活性高.     

静态存储器中子单粒子翻转截面的预测模型

中子是近地空间和核爆的主要辐射源之一,中子二次反应诱发的单粒子效应极大地影响了电子元器件的可靠性。本文针对商用体硅工艺静态存储器(SRAM)单元提出了一种中子饱和翻转截面预测模型。通过一个电路级的仿真模型,对应于辐射作用距离的线性电荷沉积(LET)效应可以通过基于SPICE仿真曲线来表现,进而用来预测翻转截面。该方法简单有效,预测结果与130 nm体硅工艺的中子实验结果吻合。     

Simulation and research on a 4T-cell based duplication redundancy SRAM for SEU radiation hardening

A novel 4T-cell based duplication redundancy SRAM is proposed for SEU radiation hardening applications. The memory cell is designed with a 65-nm low leakage process; the operation principle and the SEU radiation hardening mechanism are discussed in detail. The SEE characteristics and failure mechanism are also studied with a 3-D device simulator. The results show that the proposed SRAM structure exhibits high SEU hardening performance with a small cell size.     

22 nm FD-SOI静态随机存储器的可靠性研究

针对22 nm FD-SOI CMOS工艺静态随机存储器(SRAM),研究了工艺角、工作电压、测试温度、总剂量效应对器件性能的影响.通过自动测试设备(ATE),有效地提取了FD-SOI存储器在多种测试环境下的电学性能参数.测试结果表明,不同的工艺角对输出电平和工作状态的影响较小.随着电压的增加,静态电流随之增加,最大工...     

一种超低功耗、容错的静态随机存储器设计

为了减轻辐射环境中静态随机存储器（SRAM）受单粒子翻转（SEU）的影响以及解决低功耗和稳定性的问题,采用TSMC 90nm工艺,设计了一款可应用于辐射环境中的超低功耗容错静态随机存储器。该SRAM基于双互锁存储单元（DICE）结构,以同步逻辑实现并具有1KB（1K×8b）的容量,每根位线上有128个标准存储单元,同时具有抗SEU特性,提高并保持了SRAM在亚阈值状态下的低功耗以及工作的稳定性。介绍了这种SRAM存储单元的电路设计及其功能仿真,当电源电压VDD为0.3V时,该SRAM工作频率最大可达到2.7MHz,此时功耗仅为0.35μW;而当VDD为1V时,最大工作频率为58.2MHz,功耗为83.22μW。     

基于SRAM软错误失效概率的交织距离选择模型

在静态存储器(SRAM)抗辐射加固设计中,单错误纠错码(SEC)联合交织是解决空间SRAM多比特翻转(MBU)的有效方法。交织距离(ID)的选择应当使MBU分布在不同的物理字中,ID越大,电路实现越复杂,功耗和面积也越大。基于SRAM在空间产生的MBU错误图样以及数目,在已有的ID选择模型上进行修正,提出了一种精确的评估模型。     

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations

With increasing inter-die and intra-die parameter variations in sub-100-nm process technologies, new failure mechanisms are emerging in CMOS circuits. These failures lead to reduction in reliability of circuits, especially the area-constrained SRAM cells. In this paper, we have analyzed the emerging failure mechanisms in SRAM caches due to transistor V/sub t/ variations, which results from process variations. Also we have proposed solutions to detect those failures efficiently. In particular, in this work, SRAM failure mechanisms under transistor V/sub t/ variations are mapped to logic fault models. March test sequences have been optimized to address the emerging failure mechanisms with minimal overhead on test time. Moreover, we have proposed a design for test circuit to complement the March test sequence for at-speed testing of SRAMs. The proposed technique, referred as double sensing, can be used to test the stability of SRAM cells during read operations. Using the proposed March test sequence along with the double sensing technique, a test time reduction of 29% is achieved, compared to the existing test techniques with the same fault coverage. We have also demonstrated that double sensing can be used during SRAM normal operation for online detection and correction of any number of random read faults.     

面向ARINC429总线的抗辐照翻转故障测试系统

大气中的辐射效应是伴随着微电子技术进步而衍生出的新危害,是航空工业部门之前从未遇见的新的技术难题。以SRAM型FPGA所构成的ARINC429航空数据总线作为研究对象,研究其抗翻转故障效果。基于SRAM型器件搭建航空数据总线抗辐照翻转故障测试系统,评价航空器件对辐照效应防护能力。测试实验结果表明,系统能够正确响应不同类型的故障注入并经过表决器输出计算结果,实现对翻转故障加固的有效性的直观评测。