Unified built-in self-test for fully differential analog circuits

The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Automated System-Level Test Development for Mixed-Signal Circuits

While in the digital domain, test development is primarily conducted with the use of automated tools, knowledge-based, ad hoc test methods have been in use in the analog domain. High levels of design integration and increasing complexity of analog blocks within a system necessitate automated system-level analog test development tools. We outline a methodology for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. A system-level test set target in the given set of specifications, along with fault and yield coverages in terms of each targeted parameter, and testability problems are determined through the proposed methodology.     

Evolutionary derivation of optimal test sets for neural network based analog and mixed signal circuits fault diagnosis approach

Testing issues are becoming more and more important with the quick development of both digital and analog circuit industry. In this paper, we study the utilization of evolutionary algorithms for optimal input vectors derivation of neural network based analog and mixed signal circuits fault diagnosis approach and compare the results with normal method. We have introduced a new procedure which uses the n-detection test set concept and selects the input samples in a way that for each case of fault injection, there will be at least n sample to activate that fault. This procedure performs the optimization in two ways. The first one called speed method generates samples in a way that acceptable decision strength and lower training phase duration would be achieved. The second one called stamina method generates samples in a way that best decision strength and higher training phase duration would be achieved. Experimental results demonstrate that the obtained input voltages yields fault diagnosis with increased fault coverage and high decision strength.     

Fault Modeling and Simulation Using VHDL-AMS

Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.     

Fault-based testing and diagnosis of balanced filters

The test and diagnosis of fully differential analogue filters are addressed in this paper. Full coverage of hard/soft faults affecting circuit behaviour can be achieved by adjusting the tolerance window of the built-in self-test circuitry and the amplitude and frequency of the input test signal. Under a single fault assumption, the faulty active or passive component is located and the actual defective value of a faulty passive component is determined. A test generation procedure which results in maximum fault coverage and maximal diagnosis of hard/soft faults in the filter is presented. The test and diagnosis approach can be made compatible with IEEE Std 1149.1 for boundary scan testing.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Optimization-based multifrequency test generation for analog circuits

A robust test set for analog circuits has to detect faults under maximal masking effects due to variations of circuit parameters in their tolerance box. In this paper we propose an optimization based multifrequency test generation method for detecting parametric faults in linear analog circuits. Given a set of performances and a frequency range, our approach selects the test frequencies that maximize the observability on a circuit performance of a parameter deviation under the worst masking effects of normal variations of the other parameters. Experimental results are provided and validated by HSpice simulations to illustrate the proposed approach.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

基于ELM网络的模拟电路故障诊断

由于模拟电路的非线性、易受外界干扰等因素,模拟电路的故障在设备总故障中占很大的比例。因此,对模拟电路的故障诊断技术进行深入研究具有很重要的意义。文中针对雷达电路的故障进行快速有效的特征提取,采用神经网络中ELM网络建立诊断系统结构,并通过对具体电路的仿真,输出ELM网络的诊断结果。实际应用表明,该系统具有操作简便、诊断精度高的特点,达到了设计要求。     

New test structure for VLSI self-test: the structured test register (STR)

A new test structure which facilitates self-test in digital VLSI integrated circuits is presented. This test structure, termed the structured test register (STR), is constructed by adding some extra components to an otherwise standard BILBO. The advantages of this circuit in terms of increased fault coverage on both the functional and self-test parts of the circuit are described.     

Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.     

基于PSpice与LM算法的模拟电路故障诊断方法

采用小波神经网络与Levenberg-Marquardt算法相结合的方法,对模拟电路进行故障诊断;用小波对冲击响应信号进行多尺度分解,进行归一化后,提取故障特征信息作为神经网络的输入而进行分类。将PSpice与Matlab结合不但能有效的诊断模拟电路,且在收敛性和故障准确性上有了大幅提高。实验仿真表明,通过该方法构造的样本集训练出的网络稳定性高于传统方法,适用于神经网络。     

On Maximizing the Coverage of Catastrophic and Parametric Faults

The purpose of this paper is to analyze an optimization method to improve the testability of structural and parametric faults in analog circuits. The approach consists of finding an optimum sub-set of tests which maximizes the fault coverage with minimum cost. The method is based on covering a discrete set of intervals by taking advantage of strategies effectively used in digital synthesis. A simple application example is given to illustrate the proposal by studying the fault coverage obtained using different test sets on the ITC97 benchmark op-amp.     

Line coverage of path delay faults

We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition, but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus, the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits     

模拟电路故障诊断的结点电压灵敏度比值法

在证明线性电路中结点电压变化量比值等于结点电压灵敏度比值的基础上,提出了结点电压灵敏度比值法,通过结点电压变化量比值和结点电压灵敏度比值的比对确定电路的故障元件。理论分析和实验结果表明,该方法算法简单、诊断速度快,在可测点受限条件下具有较高的诊断精度,特别适合大规模线性模拟电路的故障诊断和测试。     

OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

In this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen–Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.     

一种基于神经网络的模拟电路故障诊断方法

模拟电路故障诊断一直是一项富有挑战性的研究课题。文章在简要介绍BP神经网络基本原理的基础上,以差分放大电路为例,设计并实现了基于BP算法的模拟电路故障诊断方法,建立了模拟电路故障诊断BP神经网络模型。实验表明,该模型的辨识精度高,能实现对模拟电路故障的正确诊断。     

基于神经网络与证据理论的模拟电路故障诊断

论述了利用多类电量测试信息、应用神经网络与D-S证据理论实现模拟电路故障诊断的基本原理,提出了一种基于可测点电压与不同测试频率下的电路增益经决策层信息融合的故障诊断新方法.分别利用此两类测试信息,各用一个独立的改进BP网络对电路进行初步诊断,再运用所提融合诊断算法实现故障定位.模拟实验结果表明:所提方法对硬故障与元件参数偏移较小的软故障均适用,故障定位准确率高.     

模拟电路故障诊断中的特征信息提取

在运用BP神经网络进行模拟电路故障诊断过程中,代表故障特征的网络输入至关重要。分析了常见特征信息提取和故障诊断方法,提出一种基于多测试点、多特征信息原始样本集的新方法。运用这种方法构造原始故障特征集,然后作为BP神经网络的输入对网络进行训练,仿真结果表明,通过该方法构造的样本集训练出来的网络对模拟电路故障诊断的正确率优于传统方法,证明了该方法在模拟电路故障诊断中的可行性,为模拟电路的故障诊断提供了一种新方法。     

A BIST-DFT technique for DC test of analog modules

Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-in Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults.     

Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor

We have developed an analog circuit fault diagnostic system based on Bayesian neural networks using wavelet transform, normalization and principal component analysis as preprocessors. Our proposed system uses these preprocessing techniques to extract optimal features from the output(s) of an analog circuit. These features are then used to train and test a neural network to identify faulty components using Bayesian learning of network weights. For sample circuits simulated using SPICE, our neural network can correctly classify faulty components with 96% accuracy.