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在可重构计算芯片设计初期,确定芯片的各种互连资源数目是一个关键问题.如果设计的互连资源过少,可能导致应用领域中的部分算法无法实现,而过多的互连资源会造成芯片面积的浪费.基于可重构计算的特点,分析了可重构计算的相邻连接、路由连接和近邻连接三种类型互连资源.通过建立互连资源估计的随机模型,提出了可重构计算芯片中各种互连资源数目的估计方法.仿真结果表明,该方法能够比较准确地估计各种互连资源的数目,从而指导可重构计算互连资源的设计,降低设计风险. 相似文献
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可重构计算是未来高性能计算的发展趋势,它兼具了通用计算的灵活性和专用计算的高效性,充分利用系统资源的同时,又能发挥应用程序的效率。可重构编译是推广可重构计算的关键技术,可重构编译系统能够为传统的软件编程人员提供一个体系结构透明的开发平台,并让用户真正灵活利用可重构计算平台。 相似文献
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介绍一种采用多条运算流水线技术的粗粒度动态可重构计算系统.使得能够在时间维和空间维上同时开发算法的循环级并行性。在此基础上研究了可重构器件的细织结构形式以及面向动态可重构的互连网络.并给出了在该系统上求解一般问题(如FIR)的重构与执行过程。最后,为实现算法到结构的自动化映射而初步建立了协同编译器框架并展望了在系统中融合向量技术的前景. 相似文献
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粗粒度可重构架构在能效比方面具有明显优势,然而其指令存储与传输过程的功耗代价过高.实验发现指令间具有明显的相似性,由此本文提出一种基于指令相似性的压缩技术,通过对指令的压缩、传输与解压,可以在不降低性能的前提下,优化架构的功耗和面积.针对同构和异构平台分别提出了指令分发模型和指令寄存器模型的解决方案,结合编译策略优化,最终与两种传统结构相比,面积效率比分别提升36%和181%,功耗效率比分别提升33%和118%. 相似文献
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基于可重构核的FPGA电路设计 总被引:4,自引:0,他引:4
电路系统的自适应性、紧凑性和低成本 ,促进了在嵌入式系统中软硬件的协同设计。在线可重构FPGA不仅可以满足这一要求 ,而且在可编程专用电路系统设计的验证及可靠性等方面有着良好的应用 ,文中介绍了可重构 FPGA的实现结构及评估方法 ,提出以线性矢量表征可重构 FPGA及其可重构核的研究模型 ,以及基于可重构核的模块化设计 ,认为面向分类的专用类可重构 FPGA应当是现阶段可重构 FPGA的研究主题。 相似文献
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针对网络有限测量资源与多样化测量需求之间矛盾日趋凸显的问题,该文在可重构的网络测量模型基础上,对网络测量任务部署问题进行建模,并提出一种测量任务部署算法。该算法利用测量构件复用及组合原理,高效利用网络测量资源,从而支持对多样化并发测量任务的部署。仿真实验数据显示,算法在任务部署成功率和任务部署时间性能指标上较GCTS (Task-execution Scheduling schemes based on Graph Coloring)算法均得到显著提高,任务部署成功率不低于90%。 相似文献
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面向DSP应用的可重构计算 总被引:2,自引:2,他引:0
DSP应用的特点是计算密集并适合并行处理,传统的可编程处理器与ASIC在性能和灵活性上各有优劣.因此出现了一种新的计算模式-可重构计算.由于它能将效率和灵活性很好地结合在一起,故正得到广泛的关注和研究.本文在介绍可重构计算的概念和分类的基础上,着重讨论了一些主流的可重构计算系统,分析了各类系统应用于DSP的特点,对可重构计算在计算模型,编译器,映射技术以及开发环境等方面的现状和趋势进行了探讨,并给出了自己的思考. 相似文献
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一种数据驱动的可重构计算统一编程模型 总被引:1,自引:0,他引:1
可重构计算以其优异的性能和高度的灵活性,在国际国内研究领域逐渐引起广泛的关注.然而,在研的可重构计算系统架构多种多样,编程模型多与体系结构相关,使用和移植都非常困难.本文为解决编程通用性问题,从可重构计算的基本特征出发,提出数据驱动的,支持异构任务并行计算的统一编程模型,并讨论其实现方法.该模型基于生产者-消费者通讯机制,支持多种类型的计算结点和通讯网络,具有高度的抽象性.实验结果显示,使用统一编程模型进行应用设计,在不同的架构上能够使用同样的用户程序,并且获得比纯硬件加速方式更高的加速比. 相似文献
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孙香花 《微电子学与计算机》2011,28(8)
首先介绍可重构技术以及基于过程级的动态可重构计算技术,阐述对动态可重构技术研究的理论价值,接下来介绍高清视频的标准和在社会生活中的应用,进一步介绍目前高清视频最先进的标准之一H.264,阐述国内外相关研究近况,为高清视频技术提供一种新的解决方向进行探讨. 相似文献
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电子干扰资源分配决策是一个双层规划问题,而且在复杂电磁环境下的作战过程中存在着大量的不确定因素。在综合考虑这些因素的条件下,建立了基于双层模糊机会约束混合整数规划的干扰资源优化分配模型。根据可能性测度理论得到双层混合整数规划模型,然后通过求解有限个混合整数线性规划问题,来获取模型的最优解。算例表明了方法的有效性。 相似文献
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本文提出了一种应用于数据并行和高密度计算任务的新型动态可重构协处理器——DReAC.DReAC可以独立地以并行或流水工作模式重构协处理器内部数据路径,完成主处理器分配的任务.DReAC由全局控制器、计算阵列和阵列数据缓冲区三部分组成.文中简要介绍了DReAC系统模型,并使用该模型模拟了部份典型算法在DReAC中的实现.仿真结果表明,在典型的多媒体和信号处理应用中,DReAC能够达到通用处理器的10倍以上的速度,甚至在某些应用中远优于其他可重构处理器的性能. 相似文献
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Po-Chih Tseng Chao-Tsung Huang Liang-Gee Chen 《The Journal of VLSI Signal Processing》2005,41(1):35-47
In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi. 相似文献
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提出了参数化系统级模型.该模型不依赖于具体结构,以任务布局与重构处理分离的两级结构处理任务调用,通过参数方式实现不同设计方案的硬件结构和布局算法的配置.采用SystemC语言对模型进行了建模验证,仿真结果表明,通过指定上下文的下载、配置和执行等时间开销参数,在系统级设计空间探索中,能很好地模拟动态重构协处理器. 相似文献