A Distributed Capacitance Analysis of Co-Planar Inductors for a CMOS QVCO with Varactor Tuned Buffer Stage

A quadrature voltage controlled oscillator (QVCO) topology exhibiting low power consumption and high phase noise performance at low supply voltages is presented. The QVCO buffer includes varactors to maximize the output voltage and minimize the current consumption. Microstrip theory and the principle of conservation of energy have been used to evaluate the distributed capacitances of symmetrical inductors to better predict the resonance frequency. The QVCO is implemented in a 0.25 m CMOS process from Agere Systems. The total current consumption including the buffer is 5.4 mA at 1.3 V supply, where of the QVCO uses 2.0 mA. The phase noise measures below –138 dBc/Hz at 3 MHz offset frequency over the 8.9% tuning range 1.715 GHz– 1.875 GHz.Niklas Troedsson (SM98) received the M.Sc. degree in electrical engineering in 2001, and the licentiate degree in circuit design in 2003, both from Lund University, Lund, Sweden. He is currently working towards the Ph.D. degree within the Department of Electroscience, Lund University, Sweden. His research interests include low voltage RF CMOS, integrated quadrature oscillators, and monolithic inductors.Henrik Sjöland (M98) received the M.Sc. degree in electrical engineering in 1994, and the Ph.D. degree in applied electronics in 1997, both from Lund University, Lund, Sweden. In 1999, he spent one year visiting the Abidi group at UCLA, Los Angeles, CA, as a Fulbright postdoctoral scholar. He is currently an associate professor at Lund University, Lund, Sweden. His research interests include the design and analysis of analog integrated circuits, feedback amplifiers, and RF CMOS. Dr. Sjöland is the author of Highly Linear Integrated Wideband Amplifiers (Kluwer, Boston, MA: 1999).     

A CMOS Backgate-Coupled QVCO Based on Back-to-Back Series Varactor Configuration for Minimal AM-to-PM Noise Conversion

A 3.3 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with very low phase noise is presented. The back-to-back series varactor configuration is employed in the LC tank for minimizing the AM-to-PM noise conversion. The backgate coupling for quadrature phase inter-locking further eliminates the noise contribution from coupling transistors and also reduces power consumption. The implemented QVCO in 0.18 $mu{rm m}$ CMOS technology achieved very low phase noise of ${- 133}~{rm dBc}/{rm Hz}$ at 1 MHz offset, where the total power consumption is 4.4 mW from a 1.0 V supply. The chip has a very high FOM of ${- 196.6}~{rm dBc}/{rm Hz}$.      

用分布电容模型分析和优化差分电感

建立了预测片上等效寄生电容的片上电感分布电容模型.预测和解释了差分电感的自激振荡频率的差异.实测数据显示,与单端驱动模式下的相同对称电感相比,差分驱动模式电感提高最大品质因数127%,具有更大的工作频率范围.设计和验证了低寄生电容的差分电感.     

Analysis and Optimum Design of Differential Inductors Using Distributed Capacitance Model

A distributed capacitance model for monolithic inductors is developed to predict the equivalently parasitical capacitances of the inductor.The ratio of the self-resonant frequency (fSR) of the differential-driven symmetric inductor to the fSR of the single-ended driven inductor is firstly predicted and explained.Compared with a single-ended configuration,experimental data demonstrate that the differential inductor offers a 127% greater maximum quality factor and a broader range of operating frequencies.Two differential inductors with low parasitical capacitance are developed and validated.     

CMOS差分电感和串联电感对的建模与分析

该文分析了基于中芯国际0.18m CMOS工艺的差分电感和串联电感对,提出了电感在射频CMOS差分电路中的应用原则。研究了串联电感对之间的串扰效应,并提出了能准确反映互感效应、衬底容性损耗效应以及线圈间容性耦合的完整串扰模型。最后,通过对一组变间距的电感对进行测量分析,验证了该模型的准确性和适用性。     

A 2.4-GHz CMOS Monolithic VCO with an MOS Varactor

A 2.4-GHz CMOS VCO is presented employing pMOS transistors as voltage-controlled capacitances and on-chip hollow spiral inductors. The design was implemented in a standard digital 0.8m CMOS process and exhibits a 15% tuning range at 2.5 V supply voltage and 9 mA supply current. Phase-noise measurements show a phase-noise of about –118 dBc/Hz at 1 MHz from the carrier.     

Integrated Multilayered On-Chip Inductors for Compact CMOS RFICs and Their Use in a Miniature Distributed Low-Noise-Amplifier Design for Ultra-Wideband Applications

A novel multilayered vertically integrated inductor structure is developed for miniature CMOS RF integrated circuits, and its properties are investigated. The effect of mutual inductance both within and between adjacent multilayer inductors is also studied. A distributed low noise amplifier is designed by incorporating this novel inductor structure in a standard JAZZ 0.18-$mu$m RF/mixed signal CMOS process, demonstrating the significance of the proposed multilayered inductors in CMOS circuit miniaturization. The three-stage distributed amplifier occupies just 288$,times,$291 $mu$m or 0.08 mm $^{2}$ of die area, making it the smallest distributed amplifier reported to date. The circuit exhibits a relatively flat gain of 6 dB from 3.1 to 10.6 GHz with less than 0.5-dB ripple, with excellent input and output match of less than ${-}$ 12 and ${-}$25 dB, respectively. The noise figure is less than 5 dB to 14 GHz with only 2.7 dB across 8–10 GHz, while the power consumption is approximately 22 mW.      

Design of an Optimized 2.5 GHz CMOS Differential LC Oscillator with Nonlinear Analysis for MOS Varactor

The oscillation amplitude and supply current relations for a differential CMOS oscillator are derived by using an analytic method. A simplified model to predict the phase noise performance of the oscillator is developed. The large signal analysis of a nonlinear inversion mode MOS varactor is presented. The derived expressions can help to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the method has been verified by designing an LC CMOS oscillator in a 0.25 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage.     

A CMOS Active Balun Using Bond Wire Inductors and a Gain Boosting Technique

An active balun with a single-ended input and a pair of differential outputs is presented for the input stages of differential circuits. The active balun, which is composed of an input resonator and cascaded common-gate amplifiers, was implemented using 0.18-mum CMOS technology and bond wire inductors. A body-source cross-coupled configuration was used to enhance the gain of the active balun. The gain is 9.3 dB at 1.8 GHz, and the phase and the amplitude error are less than 2deg and 1 dB, respectively, in the frequency range of 1 to 2 GHz, even for a P_1dB of -2.7 dBm. The balun consumes 9 mA for 3-V supply voltage.     

一种用于数字集成系统的新型CMOS三态缓冲器的设计

三态逻辑电路已被广泛应用于VLSI数字集成系统中.现在也有很多种实现三态逻辑的方法,但它们要么输出驱动能力不足够强要么占有较大的器件面积.在研究传统三态缓冲器的基础上设计了一种新型的三态缓冲器,据我们所知,这是使用晶体管数目最少的一种三态缓冲器结构.通过SPICE仿真实验表明,所设计的三态缓冲器与传统三态缓冲器相比具有更优的面积-延时积特性和更低的静态功耗.     

A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

To employ the distributed amplification technique for the design of ultra-wide-band low-noise amplifiers, the poor noise performance of the conventional distributed amplifiers (DAs) needs to be improved. In this work, the terminating resistor of the gate transmission line, a main contributor to the overall DA's noise figure, is replaced with a resistive-inductive network. The proposed terminating network creates an intentional mismatch to reduce the noise contribution of the terminating network. The degraded input matching at low frequencies can be tolerated for ultra-wide-band applications as they need to operate above 3 GHz. Implemented in a 0.13 mum CMOS process, the proposed DA achieves a flat gain of 12 dB with an average noise figure of 3.3 dB over the 3- to 9.4-GHz band, the best reported noise performance for a CMOS DA in the literature. The amplifier dissipates 30 mW from two 0.6-V and 1-V dc power supplies.     

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

In this paper, the systematic design and analysis of a CMOS performance-optimized distributed low-noise amplifier (DLNA) comprising bandwidth-enhanced cascode cells will be presented. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. The noise analysis and optimization of the DLNA accurately accounts for the impact of thermal noise of line terminations and all device noise sources of each CMOS cascode cell including flicker noise, correlated gate-induced noise and channel thermal noise on the overall noise figure. A three-stage performance-optimized wideband DLNA has been designed and fabricated in a 0.18-mum SiGe process, where only MOS transistors were utilized. Measurements of the test chip show a flat noise figure of 2.9 dB, a forward gain of 8 dB, and input and output return losses below -12 dB and -10 dB, respectively, across the 7.5 GHz UWB band. The circuit exhibits an average IIP3 of -3.55 dBm. The 872 mum times 872 mum DLNA chip consumes 12 mA of current from a 1.8-V DC voltage.     

电流反馈型均一相位噪声正交振荡器

论文提出了一种电源反馈型的全集成正交压控振荡器。得益于反馈电流源的电流调节作用,提出的正交振荡器在整个频率调谐范围之内有着均一的相位噪声 。 此振荡器用65-nm CMOS工艺实现。测试结果表明,该振荡器工作电压为1.2V, 消耗的电流均值是3mA. 频偏1MHz的相位噪声小于 -110dBc/Hz。整个调谐范围内的相位噪声变化小于1dBc/Hz, 这充分证明了电流反馈技术的正确性。     

一种用于CIS的快速低噪声CMOS缓冲器

基于TSMC0.13μm CMOS工艺,设计了一种用于CMOS图像传感器(CIS)的快速低噪声缓冲器。该缓冲器的面积相对较低,输出级采用改进式AB类输出级,不仅保证了建立速度,而且还能抑制由于电路结构不对称而带来的噪声。采用调零电阻补偿保证不同corner下的稳定性。仿真结果表明:在室温tt工艺下功耗为10μW,建立时间为8ns,低频输出噪声100dB,适用在各种高速度低功耗场合。     

A New Loss Compensation Technique for CMOS Distributed Amplifiers

This brief presents a circuit technique to compensate for the metal and substrate loss of the on-chip transmission lines (TLs), and, consequently, to improve the gain flatness and bandwidth of CMOS distributed amplifiers (DAs). An eight-stage DA suitable for 40-Gb/s optical communication is devised and implemented in a 0.13- $muhbox{m}$ CMOS process. The DA achieves a flat gain of 10 dB from dc to 44 GHz with an input and output matching better than $-$ 8 dB. The measured noise figure varies from 2.5 to 7.5 dB with the amplifier's band. The proposed DA dissipates 103 mW from two 1-V and 1.2-V dc supplies.      

基于负电容补偿技术的CMOS低噪声放大器设计

利用负电容电路补偿技术,设计了一个工作于2.4GHz频段的差分低噪声放大器。基于CHRT 0.25μm RF CMOS工艺,对电路进行仿真。与传统的共源共栅结构相比,引入负电容电路对共源管的栅漏寄生电容进行补偿,可以使放大器的匹配度、噪声系数、线性度等关键性能指标得到显著改善。仿真结果显示,该放大器的正向功率增益为17.7dB,噪声系数为1dB,IIP3为-4.9dBm,功耗为25mW,具有良好的输入输出匹配。     

一种新型低开关噪声低过冲CMOS缓冲器的设计

通过分析CMOS缓冲器过冲及开关噪声的原理,提出了一种新型的低过冲、低开关噪声的缓冲器。该缓冲器采用两种驱动级并联,降低了开关噪声。部分输出级晶体管采用缓冲器结构,控制了输出过冲。该缓冲器简单有效,不需要引入反馈结构。采用0.6 μm CMOS工艺设计,经仿真验证,电路具有良好的低开关噪声和低过冲特性。     

A Fully Differential Rail-to-Rail CMOS Capacitance Sensor With Floating-Gate Trimming for Mismatch Compensation

This paper presents a fully differential capacitance sensor employing the CBCM technique to map differential input capacitances into rail-to-rail differential output voltages. The circuit has been designed for measuring capacitances in the $pm hbox{25-fF}$ range, appropriate for sensing live cells using on-chip microelectrodes. An array architecture based on a shielded current routing bus has been developed for incorporating the capacitance measurement circuit into sensor arrays, with each pixel comprising four minimum-size digital transistors, enabling high-density integration. In addition to improving spatial resolution, the shielded current bus also eliminates the need for individual pixel calibration, conserves sensor evaluation speed, and provides protection from junction leakage. The sensor employs a 3-phase clocking scheme that enables on-chip gain tuning. The paper also presents a modified version of the sensor circuit incorporating floating-gate transistors for mismatch compensation and output offset cancellation, performed using a combination of impact-ionized channel hot electron injection and Fowler–Nordheim tunneling mechanisms. Chips comprising both versions of the sensor circuits in test arrays employing the shielded current routing bus were fabricated in a commercially available 2-poly, 3-metal, 0.5-$mu{hbox {m}}$ CMOS process. The sensor operation was demonstrated by measuring on-chip test capacitances comprising single and interdigitated metal electrodes, configured using different capacitance compensation schemes. The differential sensor in combination with the shielded current bus exhibits a maximum sensitivity of 200 mV/fF, a resolution of 15 aF, and an output dynamic range of 65 dB.      

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.     

片式电感器筛选方法

概述了电感器的发展历程,重点介绍模压片式电感器、叠层片式电感器的结构特点,以及工艺条件对固有可靠性的影响,并对以上两种类型电感器主要失效模式及其失效机理进行了简要分析,针对电感器三种主要失效模式:电性能参数退化、开路、短路,设计了模压片式和叠层片式电感器的筛选方案,并取得一定效果.