A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 33.6–33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 $^{11} -$1 PRBS. The measured bit error rate is less than $10^{-8}$ for a 33.72 Gb/s, 2$^{7} -$1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.      

低电压低功耗CMOS 5Gb/s串行收发器

设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12.     

低电压低功耗CMOS 5Gb/s串行收发器

设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12.     

A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS

A 16-256 state coarse-grain reconfigurable Viterbi accelerator fabricated in 1.3 V_t 90 nm dual-CMOS technology is described for 3.8 GHz operation, with 1.9 Gb/s data rate in 32-state mode. Radix-4 ripple-carry ACS circuits, reconfigurable path metric read/write control, and tree-bitline traceback memory circuits with programmable ring-buffer decoders enable 358 mW total power, measured at 1.3 V, 50degC, with performance scalable to 2.35 Gb/s at 1.7 V, 50degC.     

10Gb/s光收发模块封装技术

本文介绍了10Gb/s光收发模块的封装技术。准平面封装技术非常适合于大规模制造的老器件,已广泛应用于各类激光器和接收器中。     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。     

一种用于10 Gb/s Serdes的40 nm CMOS锁相环

提出了一种应用于10 Gb/s高速串并接口电路(Serdes)的高性能锁相环。采用正交压控振荡器(QVCO)实现4路等相位间隔的5 GHz时钟,输出采用2分频单转差缓冲器,实现可忽略相差的8路等相位间隔的2.5 GHz时钟。电荷泵中采用负反馈技术,以提高电流匹配性能。在SMIC 40 nm工艺下完成设计,在 1.1 V的供电电压下,锁相环的总电流为7.6 mA,输出5 GHz时钟在10 kHz~100 MHz积分范围内的均方根抖动约为107 fs,芯片尺寸仅为780 μm×410 μm。     

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 kOmega and a differential output swing of 520 mV_pp with for input spanning from to . The measured integrated input-referred noise is 3.3muA_rms. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 2³¹ - 1 PRBS input, the recovered clock jitter is and 0.7ps_rms. The retimed data exhibits 13.3 ps_pp jitter with BER . Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply.     

基于65nm工艺的3Gb/s多通道收发器*

采用 65nm工艺,实现了一款16位并行收发器的IP核,它在5pf的负载及HBM 2000V的ESD保护下,其速率为3Gb/s。为了减小延时,均衡器、时钟数据恢复电路、CRC检测电路以及8b/10b编码电路在设计中均没有使用,所以整个电路在没有电缆的情况的延时为7ns。根据收发器在工艺、电压和温度下的鲁棒特性,在设计中采用了自动频率校正的锁相环电路,低偏移的差分时钟树及具有共模反馈的稳定电流模驱动器电路。该收发器在3Gbps速度下误码率小于10^-15,可以在不同的工艺角和极端温度下正常工作,并且能够容忍20%电压的偏差变化,在100nm下的具有低延时和高稳定性的高性能处理器中能够得到很好的应用。     

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10^-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.     

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm/sup 2/ experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W.     

CMOS光接收机宽带前置放大器的设计

采用TSMC0.18μmCMOS工艺设计了光接收机宽带前置放大器。该前置放大器采用具有反馈特性的跨阻放大器实现,采用了RGC(RegulatedCasacoe)电路作为输入级,同时在电路中引入电感并联补偿的技术,以拓展前置放大器的带宽。仿真结果表明:1.8V单电压源供电情况下,电路功耗15.2mW,中频互阻增益为58.4dBΩ,-3dB带宽可达到10.2GHz,可工作在10Gb/s速率。     

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2$times$-oversampling phase-tracking CDR, implemented in 90$,$nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of ${pm }{hbox{615~ppm}}$ between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate ${≪} hbox{10}^{-12}$ was verified up to 38 Gb/s using a 2$ ^{7} -$1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90$~$nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 ${hbox{mm}}^{2}$ .      

1.25 Gb/s低功耗CMOS光接收机限幅放大器

设计并实现了用于光纤用户网和千兆以太网光接收机的限幅放大器。电路采用有源电感负载来拓展带宽、稳定直流工作点 ,通过直接耦合技术来提高增益、降低功耗。测试结果表明 ,在从 5 m Vp- p到 5 0 0 m Vp- p,即40 d B的输入动态范围内 ,在 5 0 Ω负载上的单端输出电压摆幅稳定在 2 80 m Vp- p。在 5 V电源电压下 ,功耗仅为1 30 m W。电路可稳定工作在 1 5 5 Mb/s、62 2 Mb/s、1 .2 5 Gb/s三个速率上。     

0.18μm CMOS 10Gb/s光接收机限幅放大器

利用TSMC 0.18μm CMOS工艺设计了应用于SDH系统STM-64(10 Gb/s)速率级光接收机中的限幅放大器.该放大器采用了改进的Cherry-Hooper结构以获得高的增益带宽积,从而保证限幅放大器在10Gb/s以及更高的速率上工作.测试结果表明,此限幅放大器在10Gb/s速率上,输入动态范围为42dB(3.2mV~500mV),50Ω负载上的输出限幅在250mV,小信号输入时的最高工作速率为12Gb/s.限幅放大器采用1.8 V电源供电,功耗110mW.芯片的面积为0.7mm×0.9mm.     

光通信用宽动态范围10 Gb/s CMOS跨阻前置放大器

采用UMC 0.13 μm CMOS工艺,设计了一种应用于SDH系统STM-64(10 Gb/s)光接收机前置放大器.该前置放大器采用具有低输入阻抗特点的RGC形式的跨阻放大器实现.同时,引入消直流电路来扩大输入信号的动态范围.后仿真结果表明:双端输出时中频跨阻增益约为57.6 dBΩ,-3 dB带宽为10.7 GHz,平均等效输入噪声电流谱密度为18.76 pA/sqrt(Hz),1.2V单电压源下功耗为21 mW,输入信号动态范围40 dB(10 μA～1 mA).芯片面积为0.462 mm×0.566 mm.     

10Gb/s 0.18μm CMOS光接收机前端放大电路

介绍了利用TSMC 0.18μm CMON工艺设计的应用于SDH STM-64速率级(10Gb/s)光接收机前端放大电路。该电路由前置放大器和作为主放大器的限幅放大器构成,其中前置放大器采用RGC形式的互阻放大器实现,限幅放大器采用改进的Cherry—Hooper结构。模拟结果表明该电路可以工作在10Gb/s速率上。     

具有连续自动温度补偿功能的10Gb/s光收发模块

设计并制作了一种10Gb/s光收发模块,在宽温度范围内能够保持稳定的光功率和消光比。基于背电流和光功率的换算比例,计算其偏置电流修正值和调制电流修正值,实现了光模块运行过程中激光器的工作参数可自动连续调节。通过高速电路信号仿真设计,解决了信号完整性、串扰和电磁兼容等问题。光模块收发通道可以独立工作,传输速率可达10Gb/s,实现了光模块高速率、高稳定性以及小体积设计,为甚短距离高速数据传输和处理提供了高可靠性的数据链接。     

2.5Gb/s 16:1MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2.     

应用于subLVDS接口的1.5Gb/s收发器设计

介绍了subLVDS接口的系统结构并给出一种改进的内部收发器实现电路.为了稳定直流工作点,在发送器内部加入与电源电压无关的自偏置电压源和共模负反馈电路;通过轨到轨预放大器,接收器的共模输入电压可以达到电源至地的范围.SMIC0.18μm 1P6M的工艺下,仿真结果表明该系统对随机输入数据的工作速度可以达到1.5Gb/s,工作温度范围为-40～120℃.