Degradation induced by TID radiation and hot-carrier stress in 130-nm short channel PDSOI NMOSFETs

Hot-carrier reliability for devices operating in radiation environment must be considered. In this paper, we investigate how total ionizing dose impacts the hot-carrier reliability of partially-depleted SOI I/O NMOSFETs, highlighting the effect of buried oxide. Firstly, radiation-induced damage on short channel SOI devices with 100 nm thick Si film was investigated. After low total dose irradiation, incomplete fully-depleted state has been formed due to the non-uniformly distributed positive charges in the buried oxide. Furthermore, as the dominated factor of hot-carrier injection, the body current reduces after irradiation. Subsequently, the irradiated SOI devices were subjected to hot-carrier stress for 9000-s long time. Compared with unirradiated devices, the irradiated samples display enhanced hot-carrier degradation. We attribute this phenomenon to that radiation lowers the barrier for hot-carrier injection. Therefore, in order to ensure the reliability of SOI devices operating in harsh radiation environments, SOI devices with higher quality or corresponding hardness design should be taken.     

Degradation of the parameters of transistor temperature sensors under the effect of ionizing radiation

The influence of the effective concentration of an impurity specifying the conduction type of the base region and the base thickness on the radiation resistance of transistor temperature sensors is investigated. The dependences of the forward voltage drop at the emitter transistor junction and current amplification factor on the magnitude of electron, neutron, and γ-quanta flows are revealed. It is found that degradation of the forward voltage drop under the effect of ionizing radiation begins at doses higher by almost two orders of magnitude than the current amplification factor depending on the transistor’s design features. The reproducibility of the temperature-sensitive parameter, which increases the yield percentage of suitable devices, increases after annealing of the electron-irradiated structures.     

The base current degradation of poly-emitter BJTs under AC stress

A simple model for the analysis of the ac stress effect in poly-emitter bipolar transistors is presented. Apart from the reverse-bias induced hot-carrier effects, the forward-bias recovery effect is a key factor under ac stress, it obviously suppresses the base current degradation of the device which is caused during the reverse-bias periods. In this work, we derived the relationship between the excess base current and the stress time for different ac stress conditions. This model is verified with experimental results.<>     

A new "mixed-mode" reliability degradation mechanism in advanced Si and SiGe bipolar transistors

A new mixed-mode base current degradation mechanism is identified in bipolar transistors for the first time, which, at room temperature, induces a large I/sub B/ leakage current only after simultaneous application of both high J/sub C/ and high V/sub CB/. This new mechanism differs fundamentally from well-known I/sub B/ degradation mechanisms such as the reverse EB voltage stress, high forward current stress and damage due to ionizing radiation. Extensive measurements and two-dimensional (2-D) simulations have been used to help understand the device physics associated with this new degradation mechanism.     

不同类型双极晶体管抗辐照性能的研究

时于制作工艺相同的NPN和LPNP两种类型的双极型晶体管进行了辐照实验,研究了不同类型双极晶体管的电离总剂量辐射损伤机理和退火效应。实验结果表明：在相同的辐照总剂量下．LPNP型双极晶体管的归一化电流增益的下降比NPN型双极晶体管的下降多．说明LPNP型双极晶体管的辐照敏感性更强。这与NPN和LPNP这两种类型的双极晶体管的辐射损伤机理的不同有关。对于NPN型双极晶体管,电离辐照总剂照效应主要是造成氧化物正电荷的积累：而对于LPNP型双极晶体管．电离辐照总剂量效应主要是造成界面态密度的增加。     

Radiation-dependent hot-carrier effects

The effect of ionizing radiation on hot-carrier degradation for n-channel MOSFET's has been investigated. It has been experimentally found that hot-carrier degradation for these devices increases after exposure to ionizing radiation. Exposure can be deliberate or occur during device fabrication. The cause of the enhanced degradation has been attributed to radiation-induced trap states.     

Impact of snapback-induced hole injection on gate oxide reliabilityof N-MOSFETs

N-channel MOSFETs associated with CMOS output driver circuits are often driven deep into snapback during electrostatic discharge (ESD) events. The charge-pumping technique is used to show significant hole trapping in the oxide resulting from snapback bias conditions. Floating-gate measurements verify that significant hole current flows through the oxide during snapback. It is noted that snapback-induced hole injection can dramatically reduce gate oxide charge to breakdown and explains reduced hot-carrier lifetimes after snapback stress. Snapback stress results in oxide damage that is in many ways similar to that found during hot-carrier stress and radiation damage. These long-term reliability concerns limit the maximum allowable snapback current     

电离辐射前后双极型晶体管统计特性

双极型晶体管性能统计分布在电离辐射之后会发生变化,从辐射前对称的正态分布转化为辐射后非对称的对数正态分布,这一统计特性转化缺乏清晰的物理图像。为了从微观机理层次解释这一转化过程,通过大样本定制晶体管电离辐射效应实验,获得基极电流、界面陷阱电荷辐射前后的统计特性,发现两者统计特性转化具有一致性。基于基极电流的解析物理模型分析发现辐射前后基极电流统计特性转化源自于界面陷阱电荷统计特性转化,并基于中心极限定理给出了界面陷阱电荷辐射前后统计特性转化的物理解释,即界面缺陷面密度的分散性转化源于多个随机变量以乘积形式实现界面缺陷物理过程。     

Hot-carrier reliability in deep-submicrometer LATID NMOSFETs

The hot-carrier degradation of large angle tilt implanted drain (LATID) NMOSFETs of a 0.35 μm CMOS technology is analysed and compared to the degradation behaviour of standard LDD devices. LATID NMOSFETs are found to exhibit a significant improvement in terms of both, current drivability and hot-carrier immunity. By means of I–V characterisation and charge pumping measurements, the different factors which can be responsible for this improved hot-carrier resistance are investigated. It is shown that this must be attributed to a reduction of the maximum lateral electric field along the channel, but not to a minor generation of physical damage for a given electric field or to a reduced I–V susceptibility to a given amount of generated damage.     

基于Matlab的基极电流理想因子提取方法研究

采用Matlab数字分析方法,结合多晶硅发射极双极器件基极电流的构成情况,阐述了不同理想因子电流成分分离的基本原理和数学方法。利用该方法分析了多晶硅发射极双极器件在正向大电流激励下的电参数退化过程中不同理想因子基极电流的变化情况,分析了导致各电流分量变化的物理机制。该理想因子提取方法普遍适用于各类双极型器件。     

国产pnp双极晶体管在宽总剂量范围辐照下的ELDRS

研究了不同偏置条件下国产商用pnp型双极晶体管在宽总剂量范围内的辐射损伤特性和变化规律.实验结果表明,在100 rad(Si)/s和0.01 rad(Si)/s剂量率辐照下,总累计剂量达到200 krad (Si)时,这一宽总剂量范围内辐射损伤趋势均随着总剂量值不断累积而增大,且并未出现饱和.相同剂量率辐照下,发射结施加反偏状态时国产商用pnp双极晶体管的过剩基极电流变化最大,正偏下最小,零偏介于二者之间.两款晶体管均表现出明显的低剂量率损伤增强效应(ELDRS),且在反偏下ELDRS更显著.并对出现这一实验结果的损伤机理进行了探讨.     

Hot carrier degradation of n-channel MOSFETs characterized by agated-diode measurement technique

The gated-diode measurement technique characterizes the physical damage induced in n-channel MOSFETs during hot-carrier stress. The results show that the gate oxide in the channel region is not affected by hot-carrier stress. The most severe damage is located in the gate oxide above the drain-gate overlap region. Furthermore, the measurements show that the density of generation centers in the substrate is increased after hot-carrier stress     

AC versus DC hot-carrier degradation in n-channel MOSFETs

The origins of the enhanced AC hot-carrier stress damage are examined. The enhancement in hot-carrier stress damage under AC stress conditions observed with respect to damage under DC stress conditions can fully be explained by the presence of three damage mechanisms occurring during both DC and AC operation: interface states created at low and mid-gate voltages, oxide electron traps created under conditions of hole injection into the oxide, and oxide electron traps created under conditions of hot-electron injection. It is shown that the quasi-static contributions of these mechanisms fully account for hot-carrier degradation under AC stress. The AC stress model is applied to devices from several different technologies and to several different AC stress waveforms. Excellent agreement is obtained in each case. The results demonstrate the validity of the model for frequencies up to 1 MHz. The absence of any transient effect indicates that the model could be applicable at much higher frequencies     

Precise quantitative evaluation of the hot-carrier induced drain series resistance degradation in LATID-n-MOSFETs

A method is presented which allows to distinguish the drain series resistance increase from other mechanisms contributing to the drain current degradation of hot-carrier stressed n-MOSFETs. Devices with different channel lengths but equal damages are used. The different degradation mechanisms are characterized quantitatively and a model for the drain current degradation is presented. For short stress times, the drain current degradation is dominated by series resistance degradation. For long stress times, however, the contribution of the mechanisms attributed to an “equivalent channel length increase” prevails.     

A model for AC hot-carrier degradation in n-channel MOSFETs

A recently developed model for AC hot-carrier lifetimes is shown to be valid for typical and worst-case stress waveforms found in CMOS circuits. Three hot-carrier damage mechanisms are incorporated into the model: interface states created at low and medium gate voltages, oxide electron traps created at low gate voltages, and oxide electron traps created at high gate voltages. It is shown that the quasi-static contributions of these three mechanisms fully account for hot-carrier degradation under inverterlike AC stress. No transient effects are required to explain AC stress results, at least for frequencies up to 1 MKz     

A comprehensive study of hot-carrier induced interface and oxidetrap distributions in MOSFETs using a novel charge pumpingtechnique

A novel simulation-independent charge pumping (CP) technique is employed to accurately determine the spatial distributions of interface (N_it) and oxide (N_0t) traps in hot-carrier stressed MOSFETs. Direct separation of N_it and N_0t is achieved without using simulation, iteration, or neutralization. Better immunity from measurement noise is achieved by avoiding numerical differentiation of data. The technique is employed to study the temporal buildup of damage profiles for a variety of stress conditions. The nature of the generated damage and trends in its position are qualitatively estimated from the internal electric field distributions obtained from device simulations. The damage distributions are related to the drain current degradation and well-defined trends are observed with the variations in stress biases and stress time. Results are presented which provide fresh insight into the hot-carrier degradation mechanisms     

Lifetime reliability of thin-film SOI nMOSFET's

The dc device lifetime reliability of thin-film SOI MOSFET's is investigated over a wide range of drain stress from just below the SOI breakdown voltage up to typical accelerated stress voltages. Unique hot-carrier degradation behaviors were observed for different ranges of applied drain stress. The degradation behavior and mechanism are found to dynamically change from one type observed under low drain stress (realistic operation range) to a different type observed under high drain stress (strong breakdown operation). This causes the SOI MOSFET to exhibit a two slope lifetime versus reciprocal drain voltage behavior which could have strong implications on the hot-carrier stressing methodology and reliability study of these devices     

Simulation of hot-carrier induced MOS circuit degradation for VLSIreliability analysis

A new integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance. This reliability simulation tool incorporates: (1) an accurate 1-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors; and (2) physical models for both fundamental device-degradation mechanisms (charge trapping and interface trap generation). Hot-carrier induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. A repetitive simulation scheme ensures accurate prediction of the circuit-level degradation process under dynamic operating conditions. The evolution of hot-carrier related damage in each device is automatically simulated at predetermined time intervals, instead of extrapolating the long-term degradation using only the initial simulation results. Thus, the gradual variation of dynamic stress conditions is accounted for during the long-term damage estimates     

A novel single-device DC method for extraction of the effectivemobility and source-drain resistances of fresh and hot-carrier degradeddrain-engineered MOSFET's

A new DC technique, the drain current-conductance method (DCCM), has been developed to extract the gate bias dependent effective channel mobility (μ_eff), and source and drain series resistance (R _s and R_d) of drain-engineered MOSFET's. The extraction of μ_eff, R_e, and R_d by DCCM is based on the DC measurements of drain current and conductance of a single device. The negligible difference between the measured and modeled (using the extracted parameters) linear drain current showed that the DCCM is accurate and effective for devices with different graded junction structures and channel lengths. Asymmetry between R_s and R_d for LDD p-MOSFET's was found to be more significant than for LATID n-MOSFET's. This asymmetry has invalidated many methods which utilized the assumptions of R_d=R_s for the extraction of device parameters. The DCCM was further applied to devices with nonuniform hot-carrier degradation. The μ_eff, R_s, and R_d of LATID n-MOSFET's degraded under different hot-carrier stress conditions were extracted. The increase in R_d is found to dominate the initial phase of hot-carrier degradation while the decrease in μ_eff intensifies as the stress duration increases. The extracted parameters have provided physical insight into the asymmetries of graded junctions and degradation mechanisms of hot-carrier stressed MOSFET's, The DCCM is especially useful for the extraction of SPICE parameters that are usable in circuit and reliability simulation     

X-ray lithography induced radiation damage in CMOS and bipolar devices

Radiation effects from a synchroton x-ray lithography source on the performance degradation and long term reliability of high performance self-aligned bipolar devices and deep sub-micron CMOS devices are studied. The hot-carrier properties of the x-ray induced damage in CMOS devices, such as interface states, positive oxide charges and neutral traps have been examined. The effect of these radiation induced defects and their impact on the DRAM circuits in terms of the performance and reliability are discussed. In the self-aligned, double polysilicon bipolar transistor structure interface states and trapped charges can be generated by the radiation source in the sidewall oxide near the emitter-base junction such damage can increase the emitter-base leakage current. This increase of base current can substantially degrade the device current gain at low bias.