Whole-ingot annealed semi-insulating GaAs substrates for low-noise microwave amplifiers

The quality of liquid-encapsulated Czochralski (LEC) grown GaAs substrates critically affects the final low-noise microwave device and circuit performance as evidenced by comparing Si-implanted undoped, In-alloyed, and whole-ingot annealed semi-insulating substrates. We investigated differences in Si-implant activation, electrical profiles, and uniformity of material, device, and circuit parameters. The best noise figure of 1.33 dB at 10 GHz was measured on a 0.5-µm low-noise FET fabricated on the high-pressure whole-ingot annealed LEC wafer. A noise figure of 2.0 dB with associated gain of 24 dB at 10 GHz was achieved for a monolithic two-stage low-noise amplifier (LNA) fabricated on the standard high-pressure LEC substrate.     

110-120-GHz monolithic low-noise amplifiers

The authors discuss the development of 110-120-GHz monolithic low-noise amplifiers (LNAs) using 0.1-mm pseudomorphic AlGaAs/InGaAs/GaAs low-noise HEMT technology. Two 2-stage LNAs have been designed, fabricated, and tested. The first amplifier demonstrates a gain of 12 dB at 112 to 115 GHz with a noise figure of 6.3 dB when biased for high gain, and a noise figure of 5.5 dB is achieved with an associated gain of 10 dB at 113 GHz when biased for low-noise figure. The other amplifier has a measured small-signal gain of 19.6 dB at 110 GHz with a noise figure of 3.9 dB. A noise figure of 3.4 dB with 15.6-dB associated gain was obtained at 113 GHz. The authors state that the small-signal gain and noise figure performance for the second LNA are the best results ever achieved for a two-stage HEMT amplifier at this frequency band     

A C-band high-dynamic range GaN HEMT low-noise amplifier

A C-band low-noise amplifier (LNA) is designed and fabricated using GAN HEMT power devices. The one-stage amplifier has a measured noise figure of 1.6 dB at 6 GHz, with an associated gain of 10.9 dB and IIP3 of 13 dBm. it also exhibits broadband operation from 4-8 GHz with noise figure less than 1.9 dB. The circuit can endure up to 31 dBm power from the input port. Compared to circuits based on other material and technology, the circuit shows comparable noise figure with improved dynamic range and survivability.     

Silicon implanted super low-noise GaAs MESFET

Super low-nose GaAs MESFETs have been fabricated using direct ion implantation into undoped LEC substrates. Microwave results at 12 GHz include a noise figure of 1.3 dB, with an associated gain of 10.3 dB and a maximum available gain of 14.9 dB.     

Half-micrometer gate-length ion-implanted GaAs MESFET with 0.8-dBnoise figure at 16 GHz

Ion-implanted GaAs MESFETs with half-micrometer gate length have been fabricated on 3-in-diameter GaAs substrates. At 16 GHz, a minimum noise figure of 0.8 dB with an associated gain of 6.3 dB has been measured. This noise figure is believed to be the lowest ever reported for 0.5- and 0.25-μm ion-implanted MESFETs, and is comparable to that for 0.25-μm HEMTs at this frequency. By using the Fukui equation and the fitted equivalent circuit model, a K_f factor of 1.4 has been obtained. These results clearly demonstrate the potential of ion-implanted MESFET technology for K-band low-noise integrated circuit applications     

Millimeter-wave low-noise and high-power metamorphic HEMTamplifiers and devices on GaAs substrates

This paper reports on state of-the-art HEMT devices and circuit results utilizing 32% and 60% indium content InGaAs channel metamorphic technology on GaAs substrates. The 60% In metamorphic HEMT (MHEMT) has achieved an excellent 0.61-dB minimum noise figure with 11.8 dB of associated gain at 26 GHz. Using this MHEMT technology, two and three-stage Ka-band low-noise amplifiers (LNAs) have demonstrated <1.4-dB noise figure with 16 dB of gain and <1.7 with 26 dB of gain, respectively. The 32% In MHEMT device has overcome the <3.5-V drain bias limitation of other MHEMT power devices, showing a power density of 650 mW/mm at 35 GHz, with V_ds=6 V     

X波段及DBS接收用PHEMT单片低噪声放大器

报道了X波段及DBS接收用单片低噪声放大器的研制结果。利用CAD软件对单片电路进行优化设计，设计工作包括MBE材料、PHEMT器件和单片电路三部分。在研制过程中，开展了关键工艺的专题研究。研究结果为：单级单片放大器在10：5－11．6GHz范围内，NF≤1．82dB，G≥7.72dB；在11．7－12．2GHz范围内，NF≤1．80dB，G≥6．8dB；双级放大器在10．4－11．1GHz范围内，NF≤1．96dB，G≥15．3dB，最低噪声系数为1．63dB，最高增益为16．07dB。     

High-speed, low-noise InGaP/GaAs heterojunction bipolar transistors

We have demonstrated self-aligned InGaP/GaAs heterojunction bipolar transistors (HBT's) with excellent dc, microwave, and noise performance. A 3×10 μm² emitter finger device achieved a cutoff frequency of f_T=66 GHz and a maximum frequency of oscillation of f_max=109 GHz. A minimum noise figure of 1.12 dB and an associated gain of 11 dB were measured at 4 GHz. These results are the highest combined f_T+f_max and the lowest noise figure reported for an InGaP/GaAs HBT and are attributed to material quality and the use of self-aligned base contacts. These data clearly demonstrate the viability of InGaP/GaAs HBT's for high-speed, low-noise circuit applications     

Linearity and low-noise performance of SOI MOSFETs for RFapplications

The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-ρ SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 μm FD-SOI low-noise amplifier (LNA) on high-ρ SOI substrate obtained the lowest noise figure for applications in the L and S-bands     

V-band Low-noise Integrated Circuit Receiver

A compact low-noise V-band integrated circuit receiver has been developed for space communication systems, The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.     

A design technique for a 60 GHz-bandwidth distributed basebandamplifier IC module

A DC-60 GHz, 9 dB distributed amplifier IC module is fabricated with 0.15 μm InAlAs-InGaAs low-noise HEMTs with 155 GHz f_T and 234 GHz f_max. The device is mounted in a metal package with 1.8 mm coaxial cable signal interfaces. The package is specially designed using three-dimensional electromagnetic field analyses, resulting in very flat frequency characteristics of the module within 1.5 dB gain ripples over the entire bandwidth. A multichip module loaded with two amplifier ICs in cascade is also fabricated, and operates at a 17.5 dB gain from 60 kHz to 48 GHz. The 1 dB gain compression output power is about 5 dBm for both modules. The noise figure of the single-chip module is approximately 4 dB over a 10-40 GHz frequency range     

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

In this paper, the systematic design and analysis of a CMOS performance-optimized distributed low-noise amplifier (DLNA) comprising bandwidth-enhanced cascode cells will be presented. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. The noise analysis and optimization of the DLNA accurately accounts for the impact of thermal noise of line terminations and all device noise sources of each CMOS cascode cell including flicker noise, correlated gate-induced noise and channel thermal noise on the overall noise figure. A three-stage performance-optimized wideband DLNA has been designed and fabricated in a 0.18-mum SiGe process, where only MOS transistors were utilized. Measurements of the test chip show a flat noise figure of 2.9 dB, a forward gain of 8 dB, and input and output return losses below -12 dB and -10 dB, respectively, across the 7.5 GHz UWB band. The circuit exhibits an average IIP3 of -3.55 dBm. The 872 mum times 872 mum DLNA chip consumes 12 mA of current from a 1.8-V DC voltage.     

94-GHz 0.1-μm T-gate low-noise pseudomorphic InGaAs HEMTs

Fabrication of state-of-the-art W-band 0.1-μm T-gate pseudomorphic (PM) InGaAs high electron mobility transistors (HEMTs) is reported. This device achieved a noise figure of 2.1 dB with an associated gain of 6.3 dB at 93.5 GHz. The device has a maximum gain of 9.6 dB at 94 GHz, which extrapolates to an F_max of 290 GHz. This noise figure is claimed to be the lowest ever reported for HEMTs fabricated on GaAs substrates at this frequency range     

X波段低噪声放大器的设计

为了实现X波段的低噪声放大器,介绍了按最小噪声系数设计,采用两级级联,利用Eudyna公司的HEMT晶体管设计制作的低噪声放大器。通过专用微波电路设计软件(AWR),对该电路的稳定系数、功率增益、噪声系数、驻波比、匹配网络等进行了仿真分析。根据分析结果制作的X波段LNA取得了如下指标:在9.5～10.5 GHz频带内,功率增益大于22 dB,噪声系数小于1.5 dB,输入输出驻波小于1.7。     

60-GHz pseudomorphicAl0.25Ga0.75As/In0.28Ga0.72As low-noise HEMTs

V-band low-noise planar-doped pseudomorphic (PM) InGaAs high electron mobility transistors (HEMTs) were fabricated with an indium mole fraction of 28% in the InGaAs channel. A device with 0.15-μm T-gate achieved a minimum noise figure of 1.5 dB with an associated gain of 6.1 dB at 61.5 GHz     

Manufacturing study of yield and performance dependence on gatelength of submicron AlInAs-GaInAs HEMTs

The fabrication, characterization, and statistical analysis of the performance and yield of AlInAs-GaInAs on InP low-noise high electron mobility transistors (HEMTs) with subquarter-micron T-gates fabricated with electron beam lithography are reported. This was undertaken to establish the manufacturability of submicron AlInAs-GaInAs HEMT technology for various low-noise microwave receiver applications. Excellent DC device yield (up to 90%) was obtained from devices to gate widths 300 μm and 1000 μm. A range of minimum noise figures between 0.026 to 0.5 dB at 2 GHz and 0.39 to 0.8 dB at 12 GHz were obtained for 0.15-μm and 0.20-μm gate length devices. The results establish the correlation between the noise figure and yield for this new class of microwave devices     

Design of a 40-GHz LNA in 0.13-μm SiGe BiCMOS

A low-noise amplifier (LNA) operated at 40 GHz is designed. An improved cascode configuration is proposed and the design of matching networks is presented. Short-circuited coplanar waveguides (CPWs) were used as inductors to achieve a high Q-factor. The circuit was fabricated in a 0.13-μm SiGe BiCMOS technology with a transistor transit frequency fT of 103 GHz. The chip area is 0.21 mm2. The LNA has one cascode stage with a-3 dB bandwidth from 34 to 44 GHz. At 40 GHz, the measured gain is 8.6 dB; the input return loss, S11, is-16.2 dB; and the simulated noise figure is 5 dB. The circuit draws a current of only 3 mA from a 2.5 V supply.     

W-band low-noise InAlAs/InGaAs lattice-matched HEMTs

Very low-noise 0.15-μm gate-length W-band In_0.52 Al_0.48As/In_0.53Ga_0.47As/In _0.52Al_0.48As/InP lattice-matched HEMTs are discussed. A maximum extrinsic transconductance of 1300 mS/mm has been measured for the device. At 18 GHz, a noise figure of 0.3 dB with an associated gain of 17.2 dB was measured. The device also exhibited a minimum noise figure of 1.4 dB with 6.6-dB associated gain at 93 GHz. A maximum available gain of 12.6 dB at 95 GHz, corresponding to a maximum frequency of oscillation, f_max, of 405 GHz (-6-dB/octave extrapolation) in the device was measured. These are the best device results yet reported. These results clearly demonstrate the potential of the InP-based HEMTs for low-noise applications, at least up to 100 GHz     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

A wideband low-noise amplifier (LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth,the input third intercept point (IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 /spl mu/m CMOS technology

A 24-GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18-/spl mu/m CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum noise figure of 3.9 dB at 24.3 GHz. The supply voltage and supply current are 1 V and 14 mA, respectively. To the author's knowledge, this LNA demonstrates the lowest noise figure among the reported LNAs in standard CMOS processes above 20 GHz.