Low-cost test technique using a new RF BIST circuit for 4.5-5.5 GHz low noise amplifiers

This paper presents a low-cost test technique using a new RF Built-In Self-Test (BIST) circuit for 4.5-5.5 GHz low noise amplifiers (LNAs). The test technique measures input impedance, voltage gain, noise figure, input return loss and output signal-to-noise ratio of the LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The BIST circuit contains test amplifier and RF peak detectors. The complete measurement set-up contains LNA with BIST circuit, external RF source, RF relays, 50 Ω load impedance, and a DC voltmeter. The test technique utilizes output DC voltage measurements and these measured values are translated to the LNA specifications such as input impedance and gain through the developed equations. The technique is simple and inexpensive.     

A New Approach for Built‐in Self‐Test of 4.5 to 5.5 GHz Low‐Noise Amplifiers

This paper presents a low‐cost RF parameter estimation technique using a new RF built‐in self‐test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.     

A 20-50 GHz RF MEMS single-stub impedance tuner

A novel radio-frequency (RF) microelectromechanical system (MEMS) single-stub impedance tuner has been developed. The design is based on combining the loaded line technique with the single-stub topology to obtain wide impedance coverage with high |/spl Gamma//sub MAX/|. The tuner consist of ten switched MEMS capacitors producing 1024(2/sup 10/) different impedances. The design has been optimized for noise parameter and load-pull measurements of active devices and shows excellent measured impedance coverage over the 20-50 GHz frequency range.     

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive. Jee-Youl Ryu received the BS and MS degrees in 1993 and 1997 from Pukyong National University in Electronic Engineering, Pusan, South Korea respectively. He also received the PhD degree in 2004 from Arizona State University in Electrical Engineering, Arizona, USA. He is currently with Samsung SDI Co., Ltd. His current research interests include RF IC design and testing, MMIC design and testing, analog IC design and testing, passives modeling, testing and analysis, and MEMS technology. Dr. Bruce Kim received the B.S.E.E. degree from the University of California, Irvine in 1981, the M.S. degree in electrical engineering from the University of Arizona in 1985, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in 1996. He was an Associate Professor at Arizona State University until 2005. Currently, he is an Associate Professor at The University of Alabama. His current research interests include RF IC testing, MEMS integration and VLSI circuits. He has been working on SiP testing technologies, package electrical modeling, and measurements of RF IC packages. Dr. Kim is a 1997 recipient of the National Science Foundation's CAREER Award and received the Meritorious Award from IEEE. He serves as the Chair of the IEEE CPMT Society TC-Electrical Test, associate editor of the IEEE Transactions on Advanced Packaging, associate editor of Design and Test of Computers, and program committee member of Electronic Components and Technology Conference. He is a senior member of IEEE.     

等离子体显示器产业的最新进展

综述了彩色等离子体显示器（PDP）产业的最新进展和世界各公司对PDP显示器市场的分析和预测,指出了PDP显示器已成为世界显示器件继CRT和TFT－LCD之后的又一大规模投资热点,制约PDP显示器普及的价格问题将随着技术的进步和生产规模的扩大逐步得到解决,DPD显示器产业已成为平板显示领域中最具有活力的产业之一。     

等离子体显示板面光源的制备技术及光电特性研究

利用等离子体显示板自发光、薄型、亮度高、发光均匀的特点,开发出基于等离子体显示机理的薄型等离子体面光源,用于需要薄型照明的特定场合.为克服等离子体显示板发光效率过低的不足,对面光源显示板的结构、材料,工艺和驱动电路诸方面进行多项改进,经改进后的等离子体面光源最小厚度不大于4 mm,亮度350 cd/m2,色温为 6500 K,发光效率4Lm/W.光源型 PDP 显示板的研究结果对进一步提高图象型 PDP 显示板的光电性能提供了有益的启示.     

Full software analysis and impedance matching of radio frequencyCMOS integrated circuits

We present a systematic analysis technique of complementary metal-oxide-semiconductor (CMOS) radio-frequency (RF) integrated circuits (ICs). A full simulation program with integrated circuit emphasis (SPICE) simulation of the whole chip including the package and the die, with the parameters extracted from purely software analysis, has been performed. It is shown that the RF impedance matching without S-parameter based techniques is possible and the measured results agree well with our SPICE-only software based technique     

Optimization of input impedance and mechanism of noise suppressionin a DC SQUID RF amplifier

The optimal input impedance and noise of a DC SQUID RF amplifier at frequencies of the order of 1 GHz with a resonant input matching circuit have been studied analytically, numerically, and experimentally. A model for noise temperature and power gain has been developed for the practical resonant input tank circuit. A new effect of the output noise increasing or decreasing with changing the sign of voltage-to-flux transfer coefficient has been observed experimentally and explained analytically. The different values of noise temperature for the opposite dV/dΦ values have been interpreted using a model with partially correlated current and voltage noise sources. The equivalent layout for optimal input matching of a SQUID amplifier comprising series and parallel resonant circuits has been presented. Using such a matching circuit and SIS junction as a signal source the SQUID amplifier noise temperature about 1 K has been measured at 1.1 GHz     

一种用于RF LDMOS功率放大器的匹配技术

介绍了射频高功率放大器设计中RF LDMOS器件的预匹配和匹配技术.针对一款高功率RF LDMOS-FET,在器件法兰封装内为其设计了预匹配电路,并在PCB板级对其进行了输入输出匹配电路的设计,使其在工作频带内较好地匹配到50 Ω的系统参考阻抗上.仿真及测试结果表明,当频率为950 MHz时,该RF LDMOS功放的P...     

AC-PDP新型能量恢复电路的研究

在表面放电式AC-PDP驱动原理的基础上，介绍了一种新型的PDP能量恢复驱动电路。该电路利用PDP的等效固有电容和外加电感器产生谐振，以防止突然的充放电。与以前的能量恢复方法相比较，该电路能更有效地恢复由于传统的硬开关和置换电流引起的能量损失，并且结构简单，可进行不对称操作，更适合于实际应用。     

The determination of S-parameters from the poles of voltage-gain transfer function for RF IC design

A method for estimating the S-parameters of active circuits using hand analysis is introduced. This method involves the determination of S-parameters from the poles of voltage-gain transfer function. It is found that the information on the frequency responses of input/output return loss, input/output impedance, and reverse isolation is all hidden in the poles or equivalently in the denominator of the voltage-gain transfer function of a circuit system. The method has been applied to three commonly used RF circuit configurations and one fabricated CMOS wide-band amplifier to illustrate the usefulness of the proposed theory.     

等离子体显示驱动技术发展

等离子体显示技术作为平板显示技术领域重要的分支．面对激烈的市场竞争，在降低成本和提升性能方面承受着巨大的压力。由于驱动电路单元占PDP系统总成本的主要部分，因此，其技术发展变化很快。本文从驱动工作波形的优化、专用集成电路的设计、图像的处理和高分辨率的应用等方面分别介绍了等离子体显示驱动技术近年来主要的发展情况，包括在低成本的设计、显示质量的提高等方面所作的努力。其中．如何调整重置期波形以达到高速、可靠的寻址的目的是本领域的重点研究工作。     

High-speed full-resonant address energy recovery technique for plasma display panel with load-adaptive characteristic

A simple full-resonant address energy recovery technique for a plasma display panel (PDP) is proposed. It has fast recovery time by removing the GND switch and load-adaptive power saving characteristics with the help of charge-pumping operation. Test results with a 50-inch HD single-scan PDP show that less than 350 ns of recovery time is accomplished and the maximum address power can be reduced from 280 to 120W.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

CMOS active-LC bandpass filters with coupled-inductor Q-enhancement and center frequency tuning

A novel CMOS circuit for obtaining a bandpass response from a triple-coupled-inductor arrangement is presented, featuring Q-enhancement and center frequency tuning by means of vector-modulating a current flowing through one of the coupled inductors. A 0.35-/spl mu/m CMOS LC filter prototype employing the technique has been fabricated and exhibits a center frequency tuning range of 11% around 1 GHz and Q values up to 180. The input 1-dB compression point is -13 dBm with Q set to 20 and a power consumption of 12.2 mW. Additionally, an input impedance matching scheme around a spiral transformer is presented, which tracks the center frequency of the filter. The active-LC approach can be applied to higher order filter responses and find applications in tunable building blocks for agile RF front ends and multistandard radios.     

Resonant pole inverter to drive the data electrodes of AC plasma display panel

This paper proposes the use of a resonant pole inverter (RPI) as the control circuit to drive the data electrodes of an ac plasma display panel (PDP). This new application of RPI simplifies the circuit design by using fewer components, and has lower power losses than conventional driver circuits. The circuit employs two resonant MOSFETs and zero-voltage-switching technique to generate an asymmetric pulse train with moderate rising and falling time to drive the data electrodes of a PDP. The circuit also recovers the reactive energy from the PDP, like conventional energy recovery circuits. Power losses are further reduced by adding a dc offset voltage to the pulse train. The power consumptions of different driving circuits are assessed. The proposed circuit is tested on a dual-scan 42-in SVGA ac plasma display panel and is found to be practical.     

A Procedure for Decomposing the Myoelectric Signal Into Its Constituent Action Potentials?Part I: Technique, Theory, and Implementation

A technique has been developed which enables the decomposition (separation) of a myoelectric signal into its constituent motor unit action potential trains. It consists of a multichannel (via one electrode) myoelectric signal recording procedure, a data compression algorithm, a digital filtering algorithm, and a hybrid visual-computer decomposition scheme. The algorithms have been implemented on a PDP 11/34 computer. Of the four major segments of the technique, the decomposition scheme is by far the most involved. The decomposition algorithm uses a-sophisticated template matching routine and details of the firing statistics of the motor units to identify motor unit action potentials in the myoelectric signal, even when they are super-imposed with other motor unit action potentials. In general, the algorithms of the decomposition scheme do not run automatically. They require input from the human operator to maintain reliability and accuracy during a decomposition.     

A Novel RF Test Scheme Based on a DFT Method

This paper presents a new RF testing scheme based on a design-for-testability (DFT) method for measuring functional specifications of RF integrated circuits (IC). The proposed method provides the input impedance, gain, noise figure, voltage standing wave ratio (VSWR) and output signal-to-noise ratio (SNR) of a low noise amplifier (LNA). The RF test scheme is based on theoretical expressions that produce the actual RF device specifications by utilizing the output DC voltages from the DFT chip. This technique can save marginally failing chips in production testing as well as in the system, hence saving a tremendous amount of revenue from unnecessary device replacements.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

新型等离子体平板显示器放电特性研究

本文研究了具有响应频率快、亮度高、着火电压低以及成本低等特点的新型槽型结构等离子体平板显示放电单元的放电特性,并与传统的表面放电结构进行了比较.给出了不同时刻两种结构放电单元中电场、各种粒子浓度的空间分布以及各种粒子的平均浓度随时间的变化关系.在没有能量恢复电路的情况下,该结构14″实验屏的发光效率达到0.9lm/W,功耗为50W.