A New Approach to Abstracting AltPSM Lithography Requirements for IC Design Domains

This paper lays the groundwork for defining the components needed to get clean alternating phase-shifting masks (altPSM) that ensure the manufacturability of subwavelength circuit designs. The authors create an abstract set of rules that can be used to advantage in various IC CAD tool domains. A new methodology and algorithm are presented that can quickly and easily integrate altPSM into existing and future tools earlier in the IC design flow. Finally, experimental results show how the methodology and algorithm is used to debug process-aware designs and make them altPSM-compliant.Pradiptya Ghosh has a M.S. (Computer and System Engg) from Rensselaer Polytechnic Institute, New York and a B.Engg (Computer Engineering) from Delhi University, India. He is currently working on physical syntesis tool for FPGA. Previously he has worked on alternating PSM methodology and developed tools for integrating it into DFM flow. He has worked on timing and routability driven RTL floorplanning for his thesis. He did some work on global routing algorithms and their application to datapaths at SUN Microsystems and have couple of patents on them. He has also been an architect for the CAD framework and datamodel at Sun Microsystems and have couple of patent pending in that domain. He has also worked previously at Cadence at board level tool development and at Intel prototyping a floorplanning tool.     

Processor Enhancements for Media Streaming Applications

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several levels. Today, such devices present processing capabilities and bandwidth settings that are inefficient to manage scalable QoS requirements in a typical media delivery framework. In this paper, we present an impact study of such a scalable data representation optimized for QoS (Matching Pursuit 3D algorithms) on processor architectures to achieve the best performance and power efficiency. A review of state of the art techniques for processor architecture enhancement let us expect promising opportunities from the latest developments in the reconfigurable computing research field. We present here the first design steps of an efficient reconfigurable coprocessor especially designed to cope with future video delivery and multimedia processing requirements. Architecture perspectives are proposed with respect to low development cost constraints, backward compatibilty and easy coprocessor usage using an original strategy based on a hardware/software codesign methodology.Sebastien Bilavarn received the M.S. degree from Rennes University (France) in 1998 and the PhD degree in Electrical Engineering from South Brittany University in 2002. Since June 2002, he works as a post-doc fellow at Signal Processing Institute, Swiss Federal Institute of Technology (EPFL). Sebastiens research interests include design methodologies for embedded systems, reconfigurable computing and Digital Signal Processing. Currently, his work focuses on using Adaptive Computing Systems to optimise computer architectures, which is a collaboration with the Architecture Research Lab of the System Technology Labs, Intel Corporation.Eric Debes received a M.S. in Electrical and Computer Engineering from Supélec, France in 1996, a M.S. in Electrical Engineering from the Technical University Darmstadt, Germany in 1997 and a PhD in Signal Processing from the Swiss Federal Institute of Technology. Since 2001 he has been a Researcher in the Architecture Research Lab of the System Technology Labs, Intel Corporation, Santa Clara, California. Erics research interests include image and video coding and processing algorithms as well as computer architecture and parallelism. At Intel he has been working together with different processor teams and microarchitecture research groups on the definition of new media and communication features (including new SIMD and streaming instructions, multicore processors and low-power architectures) in the CPU and the chipset to provide better media application performance and end user quality of service with a given system and processor power envelope and/or energy budget. More recently Eric has been working on system-on-chip modelling, processor and system power estimation and architecture design space exploration for consumer electronics applications. He is a member of the IEEE, of the ACM and of the SPIE.Pierre Vandergheynst received the M.S. degree in physics and the Ph.D. degree in mathematical physics from the Université catholique de Louvain, Belgium, in 1995 and 1998 respectively. From 1998 to 2001, he was a Postdoctoral Researcher with the Signal Processing Laboratory, Swiss Federal Institute of Technology (EPFL), in Lausanne, Switzerland. He is now an Assistant Professor of Visual Information Processing at EPFL, where is research focuses on computer vision, data processing and mathematical tools for visual information processing. Prof. Vandergheynst is Co-Editor-in-Chief of Signal Processing and member of the IEEE.Jean-Philippe Diguet received the M.S degree and the PhD degree from Rennes University (France) in 1993 and 1996 respectively. His thesis focused on the estimation of hardware complexity and algorithmic transforms for architectural synthesis. Then he joined the IMEC in Leuven (Belgium) where he worked as a post-doc fellow on the minimization of the power consumption of memories at the system-level. From 1997 to 2002, he has been an associated professor at the South Brittany University and member of the LESTER laboratory. In 2003/04, he has initiated and created an innovating company in the domain of short range wireless communications. In 2004, he obtains a CNRS researcher position. His current work focuses on design space exploration of embedded systems, real-time scheduling in the context of hardware/software architecture configurations. Within the LESTER laboratory, he heads the “Design Trotter” team focusing on EDA methods and tools.     

Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

Monolithic integration of photodetectors, analog-to-digital converters, data storage, and digital processing can improve both the performance and the efficiency of future portable image products. However, digitizing and processing a pixel at the detection site presents the design challenge to deliver a system with the required performance at the lowest cost, not just a system with the highest performance. This paper analyzes the area-time efficiency, the area efficiency, and the energy efficiency of a mixed-signal, SIMD focal plane processing architecture that executes front-end image applications with neighborhood processing. Implementations of the focal plane architecture achieve up to 81x higher area efficiency and up to 11x higher energy efficiency when compared to traditional TI DSP chips. Higher efficiency ratings are required to maintain portability while addressing technology limitations such as interconnect wiring density, heat extraction, and battery life. Systems can be implemented with a less expensive fabrication technology by increasing the number of pixels per processing element (PPE).Currently affiliated with the Department of Electrical Engineering and Computer Science at Vanderbilt University.William H. Robinson is an Assistant Professor in the Department of Electrical Engineering and Computer Science at Vanderbilt University. He received his B.S. in electrical engineering from Florida Agricultural and Mechanical University in 1996 and his M.S. in electrical engineering from the Georgia Institute of Technology (Georgia Tech) in 1998. He received his Ph.D. in electrical and computer engineering from Georgia Tech in 2003. His research explores the system-level integration of computer architecture to understand the impact of technology on architecture design. Topics of interest include computer architecture design, VLSI design, image processing, and mixed-signal integration with applications to portable imaging devices, integrated sensor technology, and system-on-a-chip multimedia processing. He is a member of the IEEE and participates in the Computer Society, the Education Society, and the Lasers and Electro-Optics Society.D. Scott Wills is a Professor of Electrical and Computer Engineering at the Georgia Institute of Technology. He received his B.S. in Physics from Georgia Tech in 1983, and his S.M., E.E., and Sc.D. in Electrical Engineering and Computer Science from M.I.T. in 1985, 1987, and 1990, respectively. His research interests include short wire VLSI architectures, high throughput portable processing systems, architectural modeling for gigascale (GSI) technology, and high efficiency image processors. He is a senior member of the IEEE and the Computer Society and he is an associate editor of IEEE Transactions on Computers.     

Designing an Embedded Video Processing Camera Using a 16-bit Microprocessor for a Surveillance System

This paper describes the design and implementation of a hybrid intelligent surveillance system that consists of an embedded system and a personal computer (PC)-based system. The embedded system performs some of the image processing tasks and sends the processed data to the PC. The PC tracks persons and recognizes two-person interactions by using a grayscale side view image sequence captured by a stationary camera. Based on our previous research, we explored the optimum division of tasks between the embedded system and the PC, simulated the embedded system using dataflow models in Ptolemy, and prototyped the embedded system in real-time hardware and software using a 16-bit CISC microprocessor. This embedded system processes one 320 × 240 frame in 89 ms, which yields one-third of the rate of 30 Hz video system. In addition, the real-time embedded system prototype uses 5.7 K bytes of program memory, 854 K bytes of internal data memory and 2 M bytes external DRAM. Koichi Sato is a Ph.D. student in the Department of Electrical and Computer Engineering at The University of Texas at Austin. He earned his B.S. in University of Tokyo, Japan in 1993. He worked for Automotive Development Center in Mitsubishi Electric Corporation where he was involved in lane and automobile recognition in vehicle video processing products such as automatic cruise control and drowsiness detection systems. He enrolled in the current University at 1998 and received an M.S in 2000. In his Master's thesis he worked on human tracking and human interaction recognition. His current work includes velocity extraction using the TSV transform, object tracking, and 3D object reconstruction. Brian L. Evans is a tenured Associate Professor in the Department of Electrical and Computer Engineering at The University of Texas at Austin. His research and teaching efforts are in embedded real-time signal and image processing systems. In signal processing, his research group is focused on the design and real-time software implementation of ADSL and VDSL transceivers, for high-speed Internet access. In image processing, his group is focused on the design and real-time software implementation of high-quality halftoning for desktop printers, smart image acquisition for digital still cameras, and 3-D sonar imaging systems. In signal and image processing, Dr. Evans has published over 100 refereed conference and journal papers. Dr. Evans is the primary architect of the Signals and Systems Pack for Mathematica, which has been on the market since October 1995. He was a key contributor to UC Berkeley's Ptolemy Classic electronic design automation environment for embedded systems, which has been successfully commercialized by Agilent and Cadence. His BSEECS (1987) degree is from the Rose-Hulman Institute of Technology, and his MSEE (1988) and PhDEE (1993) degrees are from the Georgia Institute of Technology. From 1993 to 1996, he was a post-doctoral researcher in the Ptolemy project at UC Berkeley. He is a member of the Design and Implementation of Signal Processing Systems Technical Committee of the IEEE Signal Processing Society, and a Senior Member of the IEEE. He is the recipient of a 1997 National Science Foundation CAREER Award. J.K. Aggarwal has served on the faculty of The University of Texas at Austin College of Engineering since 1964 and is currently Cullen Professor of Electrical and Computer Engineering and Director of the Computer and Vision Research Center. His research interests include computer vision and pattern recognition focusing on human motion. A Fellow of IEEE since 1976 and IAPR since 1998, he received the Senior Research Award of the American Society of Engineering Education in 1992, the 1996 Technical Achievement Award of the IEEE Computer Society and the graduate teaching award at The University of Texas at Austin in 1992. He has served as Chairman of the IEEE Computer Society Technical Committee on Pattern Analysis and Machine Intelligence (1987--1989); Director of the NATO Advanced Research Workshop on Multisensor Fusion for Computer Vision, Grenoble, France (1989); Chairman of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition (1993), and President of the International Association for Pattern Recognition (1992--1994). He is a Life Fellow of IEEE and Golden Core member of IEEE Computer Society. He has authored and edited a number of books, chapters, proceedings of conferences, and papers.     

BER Performance of Wireless BPSK Communication System in Tunnels With and Without Traffic

The bit error rate (BER) performance for high-speed personal communication service in tunnels with and without traffic is investigated. The impulse responses of tunnels for any transmitter–receiver location are computed by shooting and bouncing ray/image techniques. By using the impulse responses of these multipath channels, the BER performance of BPSK (binary phase shift keying) system with phase and timing recovery circuits are calculated. Numerical results have shown that the multipath effect by the vehicles in the tunnel is an important factor for BER performance. In addition, the effect of space diversity techniques and decision feedback equalizer on mitigating the multipath fading is also investigated.Chien-Hung Chen was born in Kaohsiung, Taiwan, Republic of China, on 8 March 1971. He received the MSEE degree from Tamkang University in 1999. He is studying for Ph.D. degree in the Department of Electrical Engineering, Tamkang University. His current research interests include indoor wireless communications and numerical techniques in electromagnetics.Chien-Ching Chiu was born in Taoyuan, Taiwan, Republic of China, on 23 January 1963. He received the BSCE degree from National Chiao Tung University, Hsinchu, Taiwan, in 1985 and MSEE and PhD degrees from National Taiwan University, Taipei, Taiwan, in 1987 and 1991, respectively. From 1987 to1989, he served in the ROC Army Force as a communication officer. In 1992 he joined the faculty of the Department of Electrical Engineering, Tamkang University, where he is now an Professor. He was a visiting scholar at the MIT and University of Illinois, Urbana from 1998 to 1999. His current research interests include microwave imaging, numerical techniques in electromagnetics and indoor wireless communications.Shi-Cheng Hung received the MSEE degree from Tamkang University in 1998. He is now a RF engineer. His current research interests include indoor wireless communications and numerical techniques in electromagnetics.Chien-Hung Lin received the MSEE degree from Tamkang University in 2001. He is now a RF engineer. His current research interests include indoor wireless communications and numerical techniques in electromagnetics.     

Solving Out-of-Order Communication in Kahn Process Networks

The Compaan compiler framework automates the transformation of DSP applications written in Matlab into Kahn Process Networks (KPNs). These KPNs express the signal processing applications in a parallel distributed way making them more suitable for mapping onto parallel architectures. A simple instance of a generated KPN by Compaan is a Producer process that communicates with a Consumer process via a FIFO buffer, with the Consumer reading data from the FIFO using a blocking read. When the sequence of producing data is different from the sequence of consuming data, a simple FIFO is not sufficient to implement the communication. For such case, extra storage and control are needed at the consumer side. This paper presents a compile approach that determines whether a FIFO buffer is sufficient for every Producer/Consumer pair of a Compaan-generated KPN. When additional memory is required, we provide an address generation mechanism to perform the reordering and furthermore give a lower bound on the amount of memory needed to perform the reordering. The presented approach is based on the Ehrhart theoryAlexandru Turjan was born in Pitesti, Romania, on January 26, 1977. He received Dipl.Ing. degree in Electrical Engineering from the Polytechnics University of Bucharest, Romania, in 2000. During 1998-2000 he was student in Mathematics at the University of Bucharest, Romania and between 1999-2000 worked also as software engineer. Currently he is a PhD. candidate at Leiden University, the Netherlands.Bart Kienhuis received a MSEE from Delft University of Technology in 1994 and he received his Ph.D. from Delft University of Technology in 1999. During his Ph.D., he has worked at Philips Research in Eindhoven on a design methodology (the Y-chart approach) for high performance video architectures for consumer products. His primary interest is in the area of embedded system design with an emphasis on hardware/software codesign, design space exploration, and performance modeling. From 1999 until 2000, Bart Kienhuis was a Post Doc in the group of Prof. Edward A. Lee at the University of California at Berkeley. He is currently an assistant professor at Leiden University.Ed. F. Deprettere was born in Roeselare Belgium, on August 10, 1944. He is fellow of the IEEE. He received the MSc degree from the University of Ghent, Ghent, Belgium, in 1968, and the Ph.D. Degree from the Delft University of Technology, Delft, The Netherlands, in 1981. From 1980–1999 he was professor at the department of Electrical Engineering, Circuits and Systems section, Signal Processing Group. From January 1st, 2000, he is professor at the Leiden Institute of Advances Computer Sciences, Leiden University, Leiden, The Netherlands, where he is head of the Leiden Embedded Research Center. His current research interests are in system level design of embedded systems, in particular for signal, image and video processing applications, including wireless communications and multimedia. He is editor and co-editor of 4 books and several special issues of international journals. He is on the editorial board of 3 journals.     

Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions

The video compression algorithms based on the 3D wavelet transform obtain excellent compression rates at the expense of huge memory requirements, that drastically affects the execution time of such applications. Its objective is to allow the real-time video compression based on the 3D fast wavelet transform. We show the hardware and software interaction for this multimedia application on a general-purpose processor. First, we mitigate the memory problem by exploiting the memory hierarchy of the processor using several techniques. As for instance, we implement and evaluate the blocking technique. We present two blocking approaches in particular: cube and rectangular, both of which differ in the way the original working set is divided. We also put forward the reuse of previous computations in order to decrease the number of memory accesses and floating point operations. Afterwards, we present several optimizations that cannot be applied by the compiler due to the characteristics of the algorithm. On the one hand, the Streaming SIMD Extensions (SSE) are used for some of the dimensions of the sequence (y and time), to reduce the number of floating point instructions, exploiting Data Level Parallelism. Then, we apply loop unrolling and data prefetching to specific parts of the code. On the other hand, the algorithm is vectorized by columns, allowing the use of SIMD instructions for the y dimension. Results show speedups of 5x in the execution time over a version compiled with the maximum optimizations of the Intel C/C++ compiler, maintaining the compression ratio and the video quality (PSNR) of the original encoder based on the 3D wavelet transform. Our experiments also show that, allowing the compiler to perform some of these optimizations (i.e. automatic code vectorization), causes performance slowdown, demonstrating the effectiveness of our optimizations.Special Issue on Media and Communication Applications on General Purpose Processors: Hardware and Software Issues/Journal of VLSI Signal Processing Systems/Dr. Eric Debes, (Lead) Guest Editor. Contact Author: Gregorio Bernabé.Gregorio Bernabé was born in Antibes (Alpes Maritimos, France) on 21 November 1974. He received the M.S. in Computer Science from the University of Murcia (Spain) in 1997. In 1998, he joined the Computer Engineering Department of the University of Murcia, where he is an Assistant Professor as well as a Ph. D. candidate. His current research interests include video compression using the Wavelet Transform, and the development of optimizations to improve the performance of the video compression algorithms based on the 3D wavelet transform.Jose M. Garcia was born in Valencia, Spain on 9 January, 1962. He received the MS and the PhD degrees in electrical engineering from the Technical University of Valencia (Valencia, Spain), in 1987 and 1991, respectively. In 1987 he joined the Computer Science Department at the University of Castilla-La Mancha at the Campus of Albacete (Spain). From 1987 to 1993, he was an Assistant Professor of Computer Architecture. In 1994 he became an Associate Professor at the University of Murcia (Spain). From 1995 to 1997 he served as Vice-Dean of the School of Computer Science. At present, he is the Director of the Computer Engineering Department, and also the Head of the Research Group on Parallel Computing and Architecture. He has developed several courses on Computer Structure, Peripheral Devices, Computer Architecture and Multicomputer Design. His current research interests include Multiprocessors Systems, Interconnection Networks, File Systems, Grid Computing and its Application in Multimedia Systems. He has published over 45 refereed papers in different Journals and Conferences in these fields. Dr. Garcia is a member of several international associations as IEEE Computer Society, ACM, USENIX, and also a member of some European associations (Euromicro and ATI).Pepe Gonzalez received the M.S. and Ph.D. degrees from the Universitat Politecnica de Catalunya (UPC). In January 2000, he joined the Computer Engineering Department of the University of Murcia, Spain, and became an Associate Professor in June 2001. In March 2002, he joined the Intel Barcelona Research Center, where he is a Senior Researcher. Currently, Pepe is working in new paradigms for the IA-32 family, in particular, Thermal-and Power-Aware clustered microarchitectures. pepe.gonzalez@intel.com     

基于Wireless MMX技术的H.264编码器优化的研究

H.264编码技术作为最新视频编码标准其性能非常出色.但是由于它的计算量比较大,在资源有限的嵌入式环境中无法显示出其良好的性能.Intel XScale PXA272是支持WirelessMMX技术的最新的嵌入式处理器.分析了H.264编码技术,通过使用WMMX指令和流水线技术对其瓶颈函数进行了优化,有效地提高了编码速率,达到了嵌入式系统实际应用的需求.     

Intel XScale音频设备驱动设计

Intel XScale系列处理器包含AC'97控制单元.本文通过介绍AC'97音频系统及PXA255音频接口硬件实现,并研究linux 2.6内核的新特色——ALSA音频驱动体系结构,最后得以实现PXA255 ALSA驱动.     

A new architecture for 3G and WLAN integration and inter-system handover management

WLAN has strong potential to provide a perfect broadband complement to the 3G wireless systems. This has raised much interest in their integration. In this paper, a novel architecture using the Network Inter-operating Agent (NIA), and Integration Gateway (IG) is proposed to integrate the 3G systems and WLANs of various providers that may not necessarily have direct service level agreement (SLA) among them. The proposed architecture is scalable as it eliminates the need for the creation of bilateral SLA among the 3G and WLAN operators. In addition, inter-system handover (ISHO) protocols using the concept of the dynamic boundary area is proposed to support seamless roaming between 3G and WLAN. The dynamic boundary area is determined based on the speed of the user and WLAN cell size. The ISHO procedures are initiated when a mobile user enters the boundary area of the WLAN and are completed before the user leaves the coverage area of the serving WLAN. This ensures that the roaming from WLAN to 3G is transparent to the applications. The performance evaluation shows that the proposed boundary area based ISHO algorithm outperforms the existing 3G/WLAN ISHO algorithms. Shantidev Mohanty (SM’04) received his B. Tech. (Hons.) degree from the Indian Institute of Technology, Kharagpur, India and the M.S. degree from the Georgia Institute of Technology, Atlanta, Georgia, in 2000 and 2003, respectively, both in electrical engineering. He is currently a graduate research assistant with the Broadband and Wireless Networking Laboratory and a Ph.D. candidate at the School of Electrical and Computer Engineering, Georgia Institute of Technology. His current research interests include wireless networks, mobile communications, mobility management, ad-hoc and sensor networks, and cross-layer protocol design. From 2000 to 2001 he worked as a mixed signal design engineer for Texas Instruments, Bangalore, India. He worked as a summer intern for Bell Labs, Lucent Technologies, Holmdel, New Jersey, during the summers of 2002 and 2003 and for Applied Research, Telcordia Technologies, Piscataway, New Jersey, uring the summer of 2004.     

A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.Shih-Hao Wang was born in Tainan, Taiwan, R.O.C. in 1977. He received the M.S. degree in Electrical and Control Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001, where he is currently working toward the Ph.D. degree in the Institute of Electronics.His research interests are video compression and VLSI implementation.Wen-Hsiao Peng was born in Hsin-Chu, Taiwan, Republic of China, in 1975. He received the B.S. and the M.S. degrees in Electrics Engineering from National Chiao-Tung University, Hsin-Chu, Taiwan, in 1997 and 1999respectively. During 2000–2001, he was an intern in Intel Microprocessor Research Lab, U.S.A. In 2002, he joined the Institute of Electronics of National Chiao-Tung University, where he is currently a Ph.D candidate. His major research interests include scalable video coding, video codec optimization and platform based architecture design for video compression applications. Since 2000, he has been working with video coding development and implementation. He has actively contributed to the development of MPEG-4 Fine Granularity Scalability (FGS) and MPEG-21 Scalable Video Coding (Now, MPEG-4 Part 10 AVC Amd.1).Yu-Wen Hereceived his Ph.D. degree in computer application from Tsinghua University in 2002. He was a lecture of the Department of Computer Science and Technology from 2002 to 2003 in Tsinghua University. In 2004, he joined Internet Media group of Microsoft Research Asia.His research interests include video coding, transmission and embedded multimedia application systems.Guan-yi Lin was born in Kaohsiung, Taiwan in 1981. He received the B.S. degree in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2003, where he is currently working toward the M.S. degree in the Institute of Electronics.His research interests are video compression and communication systems design.Cheng-Yi Lin was born in Tainan, Taiwan in 1981. He received the B.S. degree in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2003, where he is currently working toward the M.S. degree in the Institute of Electronics.His research interests are on-chip communication and testing.Shih-Chien Chang was born in Taichung, Taiwan in 1981. He received the B.S. degree in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2003, where he is currently working toward the M.S. degree in the Institute of Electronics.His research interests are video compression and VLSI implementation.Chung-Neng Wang was born in PingTung, Taiwan, in 1972. He received the B.S. degree and Ph.D degree in computer science and information engineering from National Chiao-Tung University (NCTU), HsinChu, Taiwan in 1994 and 2003, respectively. He joined the faculty at National Chiao-Tung University in Taiwan, R.O.C in January 2003.Since 2001 he has actively participated in ISO’s Moving Picture Experts Group (MPEG) digital video coding standardization process. He has made more than 18 contributions to the MPEG committee over the past 4 years. He published over 23 technical journal and conference papers in the field of video and signal processing. His current research interests are video/image compression, motion estimation, video transcoding, and streaming.Tihao Chiangwas born in Cha-Yi, Taiwan, Republic of China, 1965. He received the B.S. degree in electrical engineering from the National Taiwan University, Taipei, Taiwan, in 1987, and the M.S. degree in electrical engineering from Columbia University in 1991. He received his Ph.D. degree in electrical engineering from Columbia University in 1995. In 1995, he joined David Sarnoff Research Center as a Member of Technical Staff. Later, he was promoted as a technology leader and a program manager at Sarnoff. While at Sarnoff, he led a team of researchers and developed an optimized MPEG-2 software encoder. For his work in the encoder and MPEG-4 areas, he received two Sarnoff achievement awards and three Sarnoff team awards.Since 1992 he has actively participated in ISO’s Moving Picture Experts Group (MPEG) digital video coding standardization process with particular focus on the scalability/compatibility issue. He is currently the co-editor of the part 7 on the MPEG-4 committee. He has made more than 90 contributions to the MPEG committee over the past 10 years. His main research interests are compatible/scalable video compression, stereoscopic video coding, and motion estimation. In September 1999, he joined the faculty at National Chiao-Tung University in Taiwan, R.O.C. Dr. Chiang is currently a senior member of IEEE and holder of 13 US patents and 30 European and worldwide patents. He was a co-recipient of the 2001 best paper award from the IEEE Transactions on Circuits and Systems for Video Technology. He published over 50 technical journal and conference papers in the field of video and signal processing.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

VLIW DSP for mobile applications

We have developed a new digital signal processor (DSP) core for handheld terminals, the SPXK5 performance and flexibility, is compatible with high-level languages, and its architecture features low-power consumption. We describe the SPXK5 architecture and its performance in DSP applications. We also consider the question of application-specific enhancements. Such architecture enhancements as add-compare-select instructions or coprocessors for the Viterbi (1995) decoding algorithm are employed in some programmable DSPs, and for video codecs, other architectures include either single-instruction multiple-data (SIMD) instructions or media coprocessors. While such application-specific enhancements are valuable when their applications are actually in use, they do nothing to enhance the performance of other applications, and the more they are added, the greater the increase in chip size and energy requirements. In other words, for handheld terminals, such enhancements need to be chosen in a careful and balanced way. We have done this in developing the SPXK5, in which a wide range of signal processing algorithms are efficiently implemented     

VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance

This paper presents the architectural design of a multicomputer interconnection network based on the use of optical technology. The performance of the system is evaluated on a set of signal processing applications. The interconnect uses Vertical Cavity Surface Emitting Lasers (VCSELs) and flexible fiber image guides to implement a physical ring topology that is logically configured as a multiring. Processors in the multicomputer are nodes on the ring and extremely high communication bandwidth is possible. Using the Laser Channel Allocation (LCA) algorithm and the Deficit Round Robin (DRR) media access protocol, the bandwidth available in the optical interconnect can be reconfigured to make efficient use of the interconnect resources. A discrete-event simulation model of the interconnect is used to examine performance issues such as throughput, latency, fairness, and the impact of reconfigurability.Roger D. Chamberlain completed the degrees BSCS and BSEE in 1983, MSCS in 1985, and DSc (computer science) in 1989 all from Washington University in St. Louis, Missouri. He is currently an Associate Professor of Computer Science and Engineering at Washington University, where he is Director of the Computer Engineering Program. Dr. Chamberlain teaches and conducts research in the areas of computer architecture, parallel computing, embedded systems, and digital design.Mark A. Franklin received his BA, BSEE and MSEE from Columbia University, and his Ph.D. in EE from Carnegie-Mellon University. He is currently a Professor in the Department of Computer Science and Engineering at Washington University in St. Louis, Missouri, and holds the Hugo F. and Ina Champ Urbauer Chair in Engineering. He founded and is former Director of the Computer and Communications Research Center.Dr. Franklin is a Fellow of the IEEE and a member of the ACM. He has been Chair of the IEEE TCCA (Technical Committee on Computer Architecture), and Vice-Chair of the ACM SIGARCH (Special Interest Group on Computer Architecture). His research areas include computer and systems architecture, ASIC and embedded processor design, parallel and distributed systems, and systems performance evaluation.Praveen Krishnamurthy received the Bachelor of Engineering degree from University of Madras (India) in 2000 and the MS degree in Computer Engineering from Washington University in St. Louis, Missouri, in 2002. He is currently a doctoral student at Washington University in St. Louis.Abhijit Mahajan received his B.E (Electronics) degree from University of Mumbai in 1998. He received is MSEE from Washington University in 2000. He is presently working with Broadcom Corporation in India. His main area of work is signal integrity and systems engineering.     

SIP-based IEEE802.21 media independent handover — a BT Intel collaboration

In this paper, we look at various mobility management protocols and handover frameworks in use in BT. We also report on the results from a collaborative proof of concept mixed network prototype for a seamless handover system using Intel’s early implementation of the IEEE802.21 media-independent handover standard. The paper reports the design, implementation and deployment issues/options of a handover mechanism using the Intel framework which includes a connection manager and mixed network IEEE802.21 adaptation layer together with BT’s SIP-based audio/video application in a heterogeneous Wi-Fi, WiMAX and Ethernet network environment.     

A Video Streaming System for Mobile Phones: Practice and Experience

This paper presents a case of video streaming system for mobile phone which has actually been implemented and deployed for commercial services in CDMA2000 1X cellular phone networks. As the computing environment and the network connection of cellular phones are significantly different from the wired desktop environment, the traditional desktop streaming method is not applicable. Therefore, a new architecture is required to suit the successfully streaming in the mobile phone environment. We have developed a very lightweight video player for use in mobile phone and the related authoring tool for the player. The streaming server has carefully been designed to provide high efficiency, reliability and scalability. Based on a specifically-designed suite of streaming protocol, the server employs an adaptive rate control mechanism which transmits the media packets appropriately into the network according to the change in network bandwidth.Hojung Cha is currently a professor in computer science at Yonsei University, Seoul, Korea. His research interests include multimedia computing system, multimedia communication networks, wireless and mobile communication systems and embedded system software. He received his B.S. and M.S. in computer engineering from Seoul National University, Korea, in 1985 and 1987, respectively. He received his Ph.D. in computer science from the University of Manchester, England, in 1991.Jongmin Lee is a Ph.D. candidiate in computer science at Yonsei University, Seoul, Korea. His research interests include wireless multimedia system, QoS architecture, multimedia communication networks. He received his B.S. and M.S. in computer science from Kwangwoon University in 1999 and 2001, respectively.Jongho Nang is a professor in the Department of Computer Science at Sogang University. He received his B.S. degree from Sogang University, Korea, in 1986 and M.S. and Ph.D. degree from KAIST, in 1988 and in 1992, respectively. His research interests are in the field of multimedia systems, digital video library, and Internet technologies. He is a member of KISS, ACM, and IEEE.Sung-Yong Park is an associate professor in the Department of Computer Science at Sogang University, Seoul, Korea. He received his B.S. degree in computer science from Sogang University, and both the M.S. and Ph.D. degrees in computer science from Syracuse University. From 1987 to 1992, he worked for LG Electronics, Korea, as a research engineer. From 1998 to 1999, he was a research scientist at Telcordia Technologies (formerly Bellcore) where he developed network management software for optical switches. His research interests include high performance distributed computing and systems, operating systems, and multimedia.Jin-Hwan Jeong received the B.S. and M.S. degrees in computer science from Korea University, Seoul, Korea, in 1997, and 1999, respectively. He is currently in Ph.D. course at Korea University. His research interests include video processing for thin devices, multimedia streaming and operating systems.Chuck Yoo received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea and the M.S. and Ph.D. in computer science in University of Michigan. He worked as a researcher in Sun Microsystems Lab. from 1990 to 1995. He joined the Computer Science and Enginnering Department, Korea University, Seoul, Korea in 1995, where he is currently a professor. His research interests include high performance network, multimedia streaming, and operating systems.Jin-Young Choi received the B.S. degree from Seoul National University, Seoul, Korea, in 1982, the M.S. degree from Drexel University in 1986, and the Ph.D. degree from University of Pennsylvania, in 1993. He is currently a professor of Computer Science and Engineering Department, Korea University, Seoul, Korea. His current research interests are in real-time computing, formal methods, programming languages, process algebras, security, software engineering, and protocol engineering.     

A Review of Audio Fingerprinting

An audio fingerprint is a compact content-based signature that summarizes an audio recording. Audio Fingerprinting technologies have attracted attention since they allow the identification of audio independently of its format and without the need of meta-data or watermark embedding. Other uses of fingerprinting include: integrity verification, watermark support and content-based audio retrieval. The different approaches to fingerprinting have been described with different rationales and terminology: Pattern matching, Multimedia (Music) Information Retrieval or Cryptography (Robust Hashing). In this paper, we review different techniques describing its functional blocks as parts of a common, unified framework. Pedro Cano received a B.Sc and M. Sc. Degree in Electrical Engineering from the Universitat Politècnica de Catalunya in 1999. In 1997, he joined the Music Technology Group of the Universitat Pompeu Fabra where he is currently pursuing his Ph.D. on Content-based Audio Identification. He has been assistant professor in the Department of Technologies of the Universitat Pompeu Fabra since 1999. His research interests and recent work include: signal processing for music applications, within a real-time voice morphing system for karaoke applications, pattern matching and information retrieval, specifically content-based audio identification. Eloi Batlle received his M.S. degree in electronic engineering in 1995 from the Politechnical University of Catalunya in Barcelona, Spain. He then joined the Signal Processing Group at the same university where he was working on robust speech recognition. He received a PhD on this subject in 1999. While he was a PhD student he also worked as a researcher at the Telecom Italia Lab during 1997. In 2000 he joined the Audiovisual Institute (a part of the Pompeu Fabra University). Currently he is a member of the Music Technology Group of the same Institute where he leads several reseach projects on music identification and similarity. In 2000 he also joined the Department of Technologies of the Pompeu Fabra University and he teaches several subjects to undergraduate and graduate students. From 2001 he is the Deputy Director of this Department. His research interests include information theory, music similary, statistical signal processing and pattern recognition. Ton Kalker was born in The Netherlands in 1956. He received his M.S. degree in mathematics in 1979 from the University of Leiden, The Netherlands. From 1979 until 1983, while he was a Ph.D. candidate, he worked as a Research Assistant at the University of Leiden. From 1983 until December 1985 he worked as a lecturer at the Computer Science Department of the Technical University of Delft. In January 1986 he received his Ph.D. degree in Mathematics. In December 1985 he joined the Philips Research Laboratories Eindhoven. Until January 1990 he worked in the field of Computer Aided Design. He specialized in (semi) automatic tools for system verification. Currently he is a member of the Processing and Architectures for Content MANagement group (PACMAN) of Philips Research, where he is working on security of multimedia content, with an emphasis on watermarking and fingerprinting for video and audio. In November 1999 he became a part-time professor in the Signal Processing Systems group of Jan Bergmans in the area of ‘signal processing methods for data protection’. He is a Fellow of the IEEE for his contributions to practical applications of watermarking, in particular watermarking for DVD-Video copy protection. His other research interests include wavelets, multirate signal processing, motion estimation, psycho physics, digital video compression and medical image processing. Jaap Haitsma was born in 1974 in Easterein, the Netherlands. He received his B.Sc. in Electronic Engineering from the Noordelijke Hogeschool Leeuwarden in 1997. He did his thesis in 1997 at the Philips Research Laboratories in Redhill, England, on the topic of: “Colour Management for Liquid Crystal Displays”. Currently he is with the Philips Research Laboratories, Eindhoven, the Netherlands, where he has been doing research into digital watermarking and fingerprinting of audio and video since late 1997. From 1999 to 2002 he was also a part-time student at the Technical University of Eindhoven, where he obtained his M.Sc. in Electronic Engineering. His areas of interest include digital signal processing, database search algorithms and software engineering.     

Network-Adaptive Video Communication Using Packet Path Diversity and Rate-Distortion Optimized Reference Picture Selection

In this paper, we present error-resilient Internet video transmission using path diversity and rate-distortion optimized reference picture selection. Under this scheme, the optimal packet dependency is determined adapting to network characteristics and video content, to achieve a better trade-off between coding efficiency and forming independent streams to increase error-resilience. The optimization is achieved within a rate-distortion framework, so that the expected end-to-end distortion is minimized under the given rate constraint. The expected distortion is calculated based on an accurate binary tree modeling with the effects of channel loss and error concealment taken into account. With the aid of active probing, packets are sent across multiple available paths according to a transmission policy which takes advantage of path diversity and seeks to minimize the loss rate. Experiments demonstrate that the proposed scheme provides significant diversity gain, as well as gains over video redundancy coding and the NACK mode of conventional reference picture selection. Yi Liang received the Ph.D. degree in Electrical Engineering from Stanford University in 2003. His expertise is in the areas of networked multimedia systems, real-time voice and video communication, and low-latency media streaming over the wire-line and wireless networks. Currently holding positions at Qualcomm CDMA Technologies, San Diego, CA, he is responsible for video and multimedia system design and development for Qualcomm's mobile station modem (MSM) chipsets. From 2000 to 2001, he conducted research with Netergy Networks, Inc., Santa Clara, CA, on voice over IP systems that provide improved quality over best-effort networks. From 2001 to 2003, he had been the lead of the Stanford - Hewlett-Packard Labs low-latency video streaming project, in which he and his colleagues developed error-resilience techniques for rich media communication over IP networks at low latency. In the summer of 2002 at Hewlett-Packard Labs, Palo Alto, CA, he developed an accurate loss-distortion model for compressed video and contributed in the development of the mobile streaming media content delivery network (MSM - CDN) that delivers rich media over 3G wireless. Yi Liang received the B. Eng. degree from Tsinghua University, Beijing, China. Eric Setton received the B.S. degree from Ecole Polytechnique, Palaiseau, France in 2001 and the M.S. degree, in Electrical Engineering from Stanford University in 2003. He is currently a Ph.D. candidate in the department of Electrical Engineering of Stanford University and is part of the Image, Video and Multimedia Systems group. Multimedia communication over wired and wireless networks, video compession and image processing are his main research interests. In 2001, he received the Carnot fellowship and the SAP Stanford Graduate fellowship. In 2003, he received the Sony SNRC fellowship. He has spent time in industry in France at SAGEM and in the United States at HP labs and at Sony Electronics. He has 4 patents pending. Bernd Girod is Professor of Electrical Engineering in the Information Systems Laboratory of Stanford University, California. He also holds a courtesy appointment with the StanfordDepartment of Computer Science and he serves as Director of the Image Systems Engineering Program at Stanford. His research interests include networked media systems, video signal compression and coding, and 3-d image analysis and synthesis. He received his M.S. degree in Electrical Engineering from Georgia Institute of Technology, in 1980 and his Doctoral degree “with highest honours” from University of Hannover, Germany, in 1987. Until 1987 he was a member of the research staff at the Institut fur Theoretische Nachrichtentechnik und Informationsverarbeitung, University of Hannover, working on moving image coding, human visual perception, and information theory. In 1988, he joined Massachusetts Institute of Technology, Cambridge, MA, USA, first as a Visiting Scientist with the Research Laboratory of Electronics, then as an Assistant Professor of Media Technology at the Media Laboratory. From 1990 to 1993, he was Professor of Computer Graphics and Technical Director of the Academy of Media Arts in Cologne, Germany, jointly appointed with the Computer Science Section of Cologne University. He was a Visiting Adjunct Professor with the Digital Signal Processing Group at Georgia Institute of Technology, Atlanta, GA, USA, in 1993. From 1993 until 1999, he was Chaired Professor of Electrical Engineering/Telecommunications at University of Erlangen-Nuremberg, Germany, and the Head of the Telecommunications Institute I, co-directing the Telecommunications Laboratory. He has served as the Chairman of the Electrical Engineering Department from 1995 to 1997, and as Director of the Center of Excellence “3-D Image Analysis and Synthesis” from 1995-1999. He has been a Visiting Professor with the Information Systems Laboratory of Stanford University, Stanford, CA, during the 1997/98 academic year. As an entrepreneur, Prof. Girod has worked successfully with several start-up ventures as founder, investor, director, or advisor. Most notably, he has been a co-founder and Chief Scientist of Vivo Software, Inc., Waltham, MA (1993–98); after Vivo's aquisition, 1998-2002, Chief Scientist of RealNetworks, Inc. (Nasdaq: RNWK); and, from 1996–2004, an outside Director of 8 × 8, Inc. (Nasdaq: EGHT). Prof. Girod has authored or co-authored one major text-book, two monographs, and over 250 book chapters, journal articles and conference papers in his field, and he holds about 20 international patents. He has served as on the Editorial Boards or as Associate Editor for several journals in his field, and is currently Area Editor for Speech, Image, Video and Signal Processing of the “IEEE Transactions on Communications.” He has served on numerous conference committees, e.g., as Tutorial Chair of ICASSP-97 in Munich and ICIP-2000 in Vancouver, as General Chair of the 1998 IEEE Image and Multidimensional Signal Processing Workshop in Alpbach, Austria, and as General Chair of the Visual Communication and Image Processing Conference (VCIP) in San Jose, CA, in 2001. Prof. Girod has been a member of the IEEE Image and Multidimensional Signal Processing Committee from 1989 to 1997 and was elected Fellow of the IEEE in 1998 ‘for his contributions to the theory and practice of video communications.’ He has been named ‘Distinguished Lecturer’ for the year 2002 by the IEEE Signal Processing Society. Together with J. Eggers, he is recipient of the 2002 EURASIP Best Paper Award.     

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing.Chao-Chih Huang was born in Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degree in electrical engineering from National Taiwan University in 2000 and 2002, respectively. In Oct 2002, he has joined the multimedia team of Realtek Taiwan, to be a system design engineer and researched on video coding algorithms. His research interests include video compression/coding and image processing.Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing.Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Simplified Modeling of a Multipole Amplifier Using All-Pass Network Functions

This paper presents a system model for the representation of amplifiers that cannot be accurately characterized by a classical two pole transfer function. The effects of higher order poles are modeled by an all-pass function added to the conventional two pole model. The accuracy of the model is demonstrated by comparing the results for a typical CMOS amplifier to those obtained from device level simulations using SPICE. This model can be easily implemented in a standard simulator and is shown to achieve fast simulation time. This model is expected to have application in system level modelling of mixed-signal circuits using conventional SPICE simulators.Yihong Dai received his B.S. and M.Eng. degrees in Electrical Engineering from Shanghai JiaoTong University, Shanghai, China in 1993 and 1996, respectively. From 1996 to 1998, he enjoyed his industrial experiences in Shanghai with semiconductor companies like Shanghai Nortel Semiconductor and Motorola Electronics (China) Shanghai Branch. Since 1998, he has been a research assistant at the Analog and Mixed-signal Laboratory of the Electrical Engineering Department of Brigham Young University working toward his Ph.D. During the summer of 1999, he was with AMI semiconductor Utah Research and Design Center where he developed a threshold voltage based CMOS voltage reference architecture. In the summer of 2001, he was with Ultra Design where he designed a reference amplifier for high speed digital-to-analog converters. His research interest includes voltage reference, reference amplifier and high speed data converters in both CMOS and GaAs processes.Donald T. Comer received the B.S, M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and the University of Santa Clara, respectively, all in electrical engineering. He began teaching at San Jose State University in 1961 and mixed his teaching and industrial work until he left San Jose State University in 1979. He has worked for California Technical Industries, IBM Corp., Mobility Systems, Precision Monolithics, Storage Technology Corp., and Analog Devices during his career. He founded the AMI Utah Research and Design Center in 1998 that specializes in MOS design. In 2002, Dr. Comer founded Ultra Design, a design center that specializes in high-frequency heterojunction circuit designs. He holds fifteen patents and has published over 50 articles dealing with solid-state and integrated circuits. He has published five textbooks in the field of large-signal and integrated circuits. He formerly held the Quentin Berg Chair at Penn State Harrisburg from 1990 to 1995. He is now a professor of electrical and computer engineering at Brigham Young University where he held the Endowed Chair of Engineering from 1995 to 1998.David J. Comer received the B.S., M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and Washington State University, respectively, all in electrical engineering. He has worked for IBM Corp., Pacific Electromagnetics, Lawrence Livermore Laboratories, and Intel Corporation. He began his teaching career at the University of Idaho and has taught at the University of Calgary and California State University, Chico. He is presently a professor of electrical and computer engineering at Brigham Young University. He served as Chairman of the Division (Dean) of Engineering at CSU, Chico and as Department Chair at BYU.While at CSU, Chico, Dr. Comer served on the statewide Engineering Liaison Committee and served as Chair of the Council of California State University Deans of Engineering.Dr. Comer has published twelve textbooks and over 60 articles in the field of circuit design. He has contributed sections to the Encyclopedia of Physical Science and Technology and holds seven patents. He was given the Professional Achievement Award at CSU, Chico and was named the Outstanding Teacher of Engineering at BYU. He has also held the College of Engineering Research Chair at Brigham Young University.Darren Korth received the B.S. and M.S. degrees in electrical engineering at Brigham Young University, Provo, Utah in 1999. He is currently pursuing a Ph.D. in electrical engineering. He served as an instructor for the Department of Electrical and Computer Engineering at Brigham Young University from 2000 to 2002. From 2001 to 2003, he also worked as a senior design engineer at UltraDesign, LLC, Provo, Utah where he researched high-speed data converter circuits. He is currently with AMI Semiconductor in their RF CMOS group.