Reliability testing of WLCSP lead-free solder joints

The interfacial reactions of solder joints between Sn-4Ag-0.5Cu solder ball and a couple of presoldered pastes (Sn-7Zn-Al(30ppm) and Sn-3Ag-0.5Cu) were investigated in wafer-level chip-scale package (WLCSP). After appropriate surface mount technology reflow processes on printed circuit boards with a Cu/OSP (organic solderability preservative) surface finish, samples were subjected to 150°C high-temperature storage (HTS) for 1,000 h of aging or 1,000 cycles of a thermal cycling test (TCT). Sequentially, cross-section analysis is scrutinized by scanning electron microscopy/energy dispersive spectrometry and energy probe microanalysis to observe metallurgical evolution in the interface and solder buck itself. It was found that the degradation of the joint shear strength after TCT is more pronounced than that of the shear strength after HTS. Fracture surface analyses of the shear tests show that the degradation of the joint strength for HTS is solely due to the influence of the interfacial IMC grain growth, while the shear strength degradation for TCT is mainly due to the coefficient thermal expansion mismatch from the thermal cycling at the chip-solder interface and can lead to the occurrence of the crack.     

Rate-dependent properties of Sn-Ag-Cu based lead-free solder joints for WLCSP

The increasing demand for portable electronics has led to the shrinking in size of electronic components and solder joint dimensions. The industry also made a transition towards the adoption of lead-free solder alloys, commonly based around the Sn-Ag-Cu alloys. As knowledge of the processes and operational reliability of these lead-free solder joints (used especially in advanced packages) is limited, it has become a major concern to characterise the mechanical performance of these interconnects amid the greater push for greener electronics by the European Union.In this study, bulk solder tensile tests were performed to characterise the mechanical properties of SAC 105 (Sn-1%wt Ag-0.5%wt Cu) and SAC 405 (Sn-4%wt Ag-0.5%wt Cu) at strain rates ranging from 0.0088 s⁻¹ to 57.0 s⁻¹. Solder joint array shear and tensile tests were also conducted on wafer-level chip scale package (WLCSP) specimens of different solder alloy materials under two test rates of 0.5 mm/s (2.27 s⁻¹) and 5 mm/s (22.73 s⁻¹). These WLCSP packages have an array of 12 × 12 solder bumps (300 μm in diameter); and double redistribution layers with a Ti/Cu/Ni/Au under-bump metallurgy (UBM) as their silicon-based interface structure.The bulk solder tensile tests show that Sn-Ag-Cu alloys exhibit higher mechanical strength (yield stress and ultimate tensile strength) with increasing strain rate. A rate-dependent model of yield stress and ultimate tensile strength (UTS) was developed based on the test results. Good mechanical performance of package pull-tests at high strain rates is often correlated to a higher percentage of bulk solder failures than interface failures in solder joints. The solder joint array tests show that for higher test rates and Ag content, there are less bulk solder failures and more interface failures. Correspondingly, the average solder joint strength, peak load and ductility also decrease under higher test rate and Ag content. The solder joint results relate closely to the higher rate sensitivity of SAC 405 in gaining material strength which might prove detrimental to solder joint interfaces that are less rate sensitive. In addition, specimens under shear yielded more bulk solder failures, higher average solder joint strength and ductility than specimens under tension.     

Impact of temperature cycle profile on fatigue life of solder joints

In this paper the influence of the temperature cycle time history profile on the fatigue life of ball grid array (BGA) solder joints is studied. Temperature time history in a Pentium processor laptop computer was measured for a three-month period by means of thermocouples placed inside the computer. In addition, Pentium BGA packages were subjected to industry standard temperature cycles and also to in-situ measured temperature cycle profiles. Inelastic strain accumulation in each solder joint during thermal cycling was measured by high sensitivity Moire interferometry technique. Results indicate that fatigue life of the solder joint is not independent of the temperature cycle profile used. Industry standard temperature cycle profile leads to conservative fatigue life observations by underestimating the actual number of cycles to failure.     

Effect of voids on the reliability of BGA/CSP solder joints

Voids in solder joints have been considered as a defect in electronics assembly. The factors that affect void formation are complex and involve the interaction of many factors. There are no established standards for void size and void area in a solder joint for it to be deemed defective. Inspection criteria have been very subjective. The effect of voids on the reliability of solder joint may depend not only on the size, but also on frequency and location. This study is focussed on investigating the effect of voids on the reliability of solder joints. The size, location and frequency effects on the reliability were studied. Testing was done by mechanical deflection testing (torsion) system and air to air thermal cycling (−40 °C/125 °C). Failures were analyzed for the failure modes by cross sectional analysis. The results indicate that voids reduce the life of the solder joint. Voids which are greater than 50% of the solder joint area, decrease the mechanical robustness of the solder joints. Small voids also have an effect on the reliability, but it is dependent on the void frequency and location.     

PCB粘弹性对QFN焊点可靠性的影响

基于动态拉伸DMA实验所获得的FR—4PCB的蠕变柔量曲线,用广义Maxwell模型表征了PCB的粘弹性蠕变松弛特性。通过有限元软件MSC Marc分别模拟了基于PCB弹性和粘弹性两种不同性质下,QFN器件在–55～+125℃热循环条件下的应力应变,并利用修正后的Coffin-Masson方程分别计算了它们的热疲劳寿命。结果表明,基于粘弹性条件下QFN焊点可靠性模拟结果更接近实际情况。     

Effect of substrate metallization on interfacial reactions and reliability of Sn-Zn-Bi solder joints

The scope of this paper covers a comprehensive study of the lead-free Sn-Zn-Bi solder system, on Cu, electrolytic Ni/Au and electroless Ni(P)/Au surface finishes. This includes a study of the shear properties, intermetallic compounds at the substrate-ball interface and dissolution of the under bump metallization. The Sn-8Zn-3Bi (wt.%) solder/Cu system exhibited a low shear load with thick IMCs formation at the interface. The dissolution of the Cu layer in the Sn-Zn-3Bi solder is higher than that of the other two Ni metallizations. It was found that the formation of a thick Ni-Zn intermetallic compound (IMC) layer at the solder interface of the electrolytic Ni bond pad reduced the mechanical strength of the joints during high temperature long time liquid state annealing. The solder ball shear-load for the Ni(P) system during extended reflow increased with an increase of reflow time. No spalling was noticed at the interface of the Sn-Zn-3Bi solder/Ni(P) system. Sn-8Zn-3Bi solder with electroless Ni(P) metallization appeared as a good combination in soldering technology.     

Effect of aging on mechanical properties of high temperature Pb-rich solder joints

The effect of aging on the evolution of interfacial microstructure and mechanical properties of Pb-rich PbSnAg solder joints with different Sn content was investigated. Tensile samples were prepared by soldering two pieces of Ni or Cu strips resulting in joints with gap sizes of about 250 μm. Multi-layered structures composed of Ni coated Si-chips soldered onto Ni/Cu metallized ceramic substrates were used for fatigue testing. All samples were subjected to thermal aging at 250 °C up to 500 h. Microstructural investigations revealed that independent from the substrate material, increased Sn content of the solder alloy results in improvement of the tensile and fatigue properties of the joints and a higher growth rate of the interfacial intermetallic compound (IMC) layers. It was found that the thickness of the wettable substrate especially in the case of low-Sn alloys, also affects the interfacial properties of high temperature PbSnAg solder joints. In this case, a reduced Sn content in solder joints results in weakening of the interface during the reflow process and subsequent thermal aging. The dominant failure mode of the solder joints subjected to cyclic loading was delamination of the interfacial IMC layer from the substrate. Finite element simulations were conducted by using a strain rate and pressure dependent material model for PbSnAg solder in order to analyse the states of stress and strain during static and cyclic loading.     

Design of experiments to investigate reliability for solder joints PBGA package under high cycle fatigue

This paper emphasizes a rapid assessment methodology using by the design of experiments (DOE) to determine fatigue life of ball grid array (BGA) components in the random vibration environment. The most critical dynamic loading occurs when the dominant frequency approaches the natural frequency of the printed wiring board (PWB) assembly. This research has chosen to work within the PWB clamped on two opposite edges. One only needs to think of commercial personal portable electronic products such as cell phones, personal data assistants, and entertainment devices (as exemplified by the I-pod) to realize that electronic products are no longer exclusively used in a relatively benign office environment. The approach in this paper will involve global (entire PWB) and local (particular component of interest) modeling approach. In the global model approach, the vibration response of the PWB will be determined. This global model will give us the response of the PWB at specific component locations of interest. This response is then fed into a local stress analysis for accurate assessment of the critical stresses in the solder joints of interest. The stresses are then fed into a fatigue damage model to predict the life. The solution is achieved by using a combination of finite element analysis (FEA) and physics of failure to BGA damage analysis.     

An investigation on thermal reliability of underfilled PBGA solder joints

The failure mechanism, as well as cycles to failure, of two groups of PBGA samples (with/without underfill) for thermal shock in the range of -40/spl square/-125/spl square/ were presented. The experiment shows that the solder ball in the samples without underfill cracked after 500 times cycle, while no crack was found in the underfilled samples even after 2700 cycles. However, the die attach layer delaminated after 500 cycles and the PCB cracked in the underfilled samples after long time cycling. C-SAM is employed to investigate the delamination in the underfilled samples. Highly concentrated stress-strain induced by the CTE mismatch between the BGA component and the PCB, coarsened grain and two kinds of intermetallic compounds (Ni/sub 3/Sn/sub 2//NiSn/sub 4/) which formed during reflow and thermal cycling and their impact on the reliability of solder joints are discussed in this paper. The initiation of the crack and its propagation are also presented in this paper. By means of dye penetrant test, the authors reveal the distribution of microcracks in the solder ball array. In addition, this paper includes results of simulation, which further verified its conclusions.     

The effect of solder paste composition on the reliability of SnAgCu joints

As the electronics industry is moving towards lead-free manufacturing processes, more effort has been put into the reliability study of lead-free solder materials. Various tin–silver–copper-based solders have become widely accepted alternatives for tin–lead solders. In this study, we have tested three different SnAgCu solder compositions. The first consisted of a hypoeutectic 96.5Sn/3.0Ag/0.5Cu solder, the second of a eutectic 95.5Sn/3.8Ag/0.7Cu solder, and the third of a hypereutectic 95.5Sn/4.0Ag/0.5Cu solder. A eutectic SnPb solder was used as a reference. The test boards were temperature-cycled (−40 to +125 °C) until all samples failed. The results of the temperature cycling test were analyzed, and cross-section samples were made of the failed joints. Scanning electron and optical microscopy were employed to analyze the fracture behavior and microstructures of the solder joints. The reliability of lead-free solders and the effect of microstructures on joint reliability are discussed.     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

无铅微焊点的热效应仿真及可靠性分析

采用Anand模型描述无铅焊点(SAC305)的力学性能,运用有限元法模拟球栅阵列封装在温度循环载荷下的应力应变响应并对其进行分析,着重对关键焊点的应变能进行了讨论。结果表明,关键焊点的关键区域出现在焊点的上表面边缘处,为最容易出现损坏的部位,并得到了实验的验证;在温度循环的过程中,升温阶段塑性应变产生速率远高于高温驻留阶段的塑性应变产生速率,极大地影响着焊点使用寿命。     

Effect of randomness of Cu-Sn intermetallic compound layerthickness on reliability of surface mount solder joints

A statistical reliability analysis on thermal fatigue lifetime of surface mount solder joints, considering randomness of Cu-Sn intermetallic compound (IMC) layer thickness, is presented. Based on published thermal fatigue life test data, the two-parameter Weibull distribution of the thermal fatigue lifetime for a fixed IMC layer thickness is found, and a K-S goodness-of-fit test is conducted to examine the goodness of fit of the assumed Weibull distribution. Then, the Weibull parameters as functions of IMC layer thickness are obtained. Considering the randomness of IMC layer thickness, the MTTF and reliability of surface mount solder joints on thermal cycles are analyzed. For surface mount solder joints formed under the same conditions and loaded during the same thermal cycling as stated in the publication, numerical results of the MTTF and reliability are presented. The results show that when the mean value of MC layer thickness is low (e.g., smaller than 1.5 μm), the effect of randomness of IMC layer thickness is significant; i.e., the MTTF has strong dependence on IMC layer thickness distribution; and the reliability is significantly different at high thermal cycles. When the mean value of IMC layer thickness is high (e.g., greater than 2.0 μm), the effect of randomness of IMC layer thickness is negligible. Therefore, the presented results are important to the reliability study of surface mount solder joints. Even though the validity of the presented results based on the test data remains to be verified from other sources of data, the proposed statistical method is generally applicable for thermal fatigue reliability analysis of surface mount solder joints. By combining the proposed method with the forming mechanism of IMC layer under varying manufacturing and loading conditions, a comprehensive reliability analysis on thermal fatigue lifetime of surface mount solder joints can be expected     

刚挠背板动力学仿真与焊点可靠性研究

根据通信设备中刚挠背板互联结构,建立了有限元模型。采用两种约束方案,通过模态分析获得其固有频率和振型;通过随机振动分析,获得其应力应变;根据Coffin-Manson经验公式,结合三带技术建立了互联焊点的振动疲劳寿命预测模型,并计算了其疲劳损伤。结果表明:备用状态下互联结构的一阶固有频率为141Hz,工作状态下为988Hz;随机振动负载条件下刚挠结合部位及焊点与刚性背板连接区为应力集中区;对备用状态下互联结构施加z方向激励,焊点的疲劳损伤最大。     

Effect of bump size on current density and temperature distributions in flip-chip solder joints

Three dimensional thermo-electrical analysis was employed to simulate the current density and temperature distributions for eutectic SnAg solder bumps with shrinkage bump sizes. It was found that the current crowding effects in the solder were reduced significantly for smaller solder joints. Hot-spot temperatures and thermal gradient were increased upon reducing the solder. The maximum temperature for solder joint with 144.7 μm bump height is 103.15 °C which is only 3.15 °C higher than the substrate temperature due to Joule heating effect. However, upon reducing the bump height to 28.9 μm, the maximum temperature in the solder increased to 181.26 °C. Serious Joule heating effect was found when the solder joints shrink. The higher Joule heating effect in smaller solder joints may be attributed to two reasons, first the increase in resistance of the Al trace, which is the main heating source. Second, the average and local current densities increased in smaller bumps, causing higher temperature increase in the smaller solder bumps.     

Effect of elevated temperature on PCB responses and solder interconnect reliability under vibration loading

In this paper, vibration tests are conducted to investigate the influence of temperature on PCB responses. A set of combined tests of temperature and vibration is designed to evaluate solder interconnect reliability at 25 °C, 65 °C and 105 °C. Results indicate that temperature significantly affects PCB responses, which leads to remarkable differences in vibration loading intensity. The PCB eigenfrequency shifts from 290 Hz to 276 Hz with an increase of test temperature from 25 °C to 105 °C, during which the peak strain amplitude is almost the same.Vibration reliability of solder interconnects is greatly improved with temperature rise from 25 °C to 105 °C. Mean time to failure (MTTF) of solder joint at 65 °C and 105 °C is increased by 70% and 174% respectively compared to that of solder joint at 25 °C. Temperature dominates crack propagation path of solder joint during vibration test. Crack propagation path is changed from the area between intermetallic compound (IMC) layer and Cu pad to the bulk solder with temperature increase.     

Effect of voids on thermo-mechanical reliability of chip resistor solder joints: Experiment,modelling and simulation

With the introduction of lead-free solder alloys, the effect of voids on solder joint reliability has rapidly gained importance. In this study, a first analysis of X-rayed CR0805 solder joints shows a significant reduction in void content, from 20% down to 2.5%, after vacuum soldering. The statistical analysis of the void distribution demonstrates that the vacuum option reduces number of voids and median diameter of voids in comparison to the convection soldering process. A subsequent accelerated thermal cycling test of these analysed test vehicles, according to JESD22-A104D, indicates the tendency of a higher characteristic life time for higher void content. In contrast to these findings, the 1% to failure criterion reveals a higher reliability for lower voiding. During the finite element method (FEM) modelling part of this study, two modelling approaches of void implementation into solder joint geometry are investigated: modelling with a constant volume of the standoff for different void contents, and a modelling approach with a random combination of void content and volume of standoff. The modelling approach with the random combination reveals that voids can reduce the lifetime in the “worst case” parameter combination. In particular, the 1% time to failure rate indicates a quantitative correlation with the experimental results. Furthermore, the FEM results suggest a higher impact on reliability for a single void in comparison to a distribution of multiple voids with similar void content. Finally, the FEM study shows a high sensitivity of predicted life time with respect to the standoff height. Based on this finding, the CR0805 solder joint geometry is examined using optical inspection and cross-section polishes with the outcome that the better wetting behaviour during vacuum soldering causes a reduction of the solder alloy volume and consequently further decreases the standoff height.     

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.     

Critical issues of wafer level chip scale package (WLCSP) withemphasis on cost analysis and solder joint reliability

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study