Observation of mobility enhancement in ultrathin SOI MOSFETs

The mobility in n-channel SOI MOSFETs exhibits a significant increase as the SOI film becomes thinner than 1000 Å. At a 500 Å SOI thickness, the mobility values are distributed in the 700-1100 cm²/Vs range, which are obviously higher than the value in a bulk MOSFET having an identical doping concentration. The observed mobility enhancement has been explained by a decrease in the vertical electric field, associated with the complete depletion of the SOI film     

Quantum-mechanical effects in trigate SOI MOSFETs

A self-consistent Poisson-Schro/spl uml/dinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm /spl times/ 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold voltage is higher than predicted by classical Poisson solvers. The current drive is diminished, and the subthreshold slope is degraded, especially in the devices with the smallest cross sections.     

On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.     

Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demonstrated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body increases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation.     

AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs

In this letter we present for the first time an ac analysis of the gate-induced floating body effects (GIFBE) occurring in ultrathin gate oxide partially depleted (PD) silicon-on-insulator (SOI ) MOSFETs due to tunneling gate current. A simple equivalent circuit is proposed, which indicates that the ac behavior of GIFBE is related to the small-signal voltage variations of the floating body region. It also shows that due to the high impedance seen by the body region toward the external nodes, the GIFBE frequency dependence is characterized by a very low cut off frequency (< a few kilohertz), which is consistent with experimental data and circuit simulations performed with BSIMSOI.     

Single-transistor latch in SOI MOSFETs

A single-transistor latch phenomenon observed in silicon-on-insulator (SOI) MOSFETs is reported. This latch effect, which occurs at high drain biases, is an extreme case of floating-body effects which are present in SOI MOSFETs. The floating body results in positive feedback between the impact ionization current, body-to-source diode forward bias, and transistor currents. At large drain voltages, this positive feedback can maintain a high-drain-to-source current even when the MOS gate is biased well below its threshold voltage     

Fabrication of ultrathin, highly uniform thin-film SOI MOSFETs withlow series resistance using pattern-constrained epitaxy

We report a novel fabrication process for self-aligned, ultrathin, highly uniform thin-film SOI MOSFETs with low series resistance. Self-aligned, ultrathin SOI n-MOSFETs with 8 nm-50 nm undoped channel were fabricated. For n-MOSFETs with a 0.2 μm effective channel length, a saturation transconductance of 242 mS/mm, and a low series resistance (R_sd/=333 Ω·μm) were obtained     

Short-channel effects in SOI MOSFETs

Short-channel effects in thin-film silicon-on-insulator (SOI) MOSFETs are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. These dependences enable control of threshold-voltage reduction, channel-charge enhancement due to a drain bias, carrier velocity saturation, channel-length modulation and its effect on output conductance, as well as device degradation due to hot carriers in short-channel SOI MOSFETs. A short-channel effect exclusive to SOI MOSFETs, back-surface charge modulation, is described. Because of the short-channel effects, the use of SOI MOSFETs in VLSI circuits provides the designer with additional flexibility as compared to bulk-MOSFET design. Various design tradeoffs are discussed     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate

This letter presents a simple low-temperature process to fabricate Schottky-barrier (SB) MOSFETs that integrates a midgap metallic gate (tungsten). The device architecture is based on a thin (10 nm) and lowly doped silicon-on-insulator film that provides a threshold voltage of -0.3 V independent on the depletion charge and therefore not sensitive to variations in film thickness and doping. A gate encapsulation technique using an SiO/sub 2/-like hydrogen silsesquioxane capping layer features 15-nm-wide spacers and ensures the compatibility with the PtSi self-aligned silicide process. Long-channel devices present an ideal subthreshold swing of 60 mV/dec, over six decades of I/sub on//I/sub off/ without any sign of sublinear upward bending of the I/sub DS/--V/sub DS/ curves at low drain voltage.     

Dopant segregation in SOI Schottky-barrier MOSFETs

We present experimental results on silicon-on-insulator Schottky-barrier MOSFETs with fully silicided NiSi source and drain contacts. Dopant segregation during silicidation was used to improve the device characteristics: on-currents, significantly higher than without dopant segregation as well as an almost ideal off-state are demonstrated in n-type as well as p-type SB-MOSFETs. Temperature dependent measurements show that the effective Schottky-barrier height in devices with segregation can be strongly lowered. In addition, we investigate the dopant segregation technique with simulations. Comparing simulations with experiments it turns out that the spatial extend of the segregation layer is on the few nanometer scale which is necessary for ultimately scaled devices. Furthermore, the use of ultrathin-body SOI in combination with ultrathin gate oxides results in an even further increased transmission through the Schottky barriers and consequently leads to strongly improved device characteristics. As a result, the dopant segregation technique greatly relaxes the requirement of low Schottky-barrier silicides for high performance transistor devices.     

Special mechanisms in thin-film SOI MOSFETs

The main special mechanisms that govern the operation of thin-film SOI MOSFETs are reviewed. The influence of the most important technological and electrical parameters, e.g. the film and buried oxide thicknesses, film and silicon substrate doping, channel length, substrate bias, and interface defects, is discussed. The electrical properties of fully depleted thin-film SOI MOS transistors are improved, especially the driving current and the subthreshold swing. We address the advantages of thin-film SOI devices in relation to scaling rules down to deep submicron transistors, as well as the main parasitic phenomena, e.g. the kink, latch, breakdown, self-heating and hot-carrier degradation effects. Finally, the low temperature properties and potential quantum effects are outlined.     

A 2-D analytical solution for SCEs in DG MOSFETs

A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs.     

Enhanced substrate current in SOI MOSFETs

This letter reports an enhanced substrate current at high gate bias in SOI MOSFETs. A comparison between coprocessed bulk and partially depleted SOI MOSFETs is used to present the enhancement unique to SOI devices and demonstrate the underlying mechanism. Other than electric field, a new source for carrier heating in the channel, i.e., self-lattice heating, is found to be responsible for the excess substrate current observed. The impact of this phenomenon on SOI device lifetime prediction and compact modeling under dynamic operating conditions typical of digital circuit operation is described. This SOI-specific enhancement must be considered in one-to-one comparisons between bulk and SOI MOSFETs regarding hot-carrier effects     

Subthreshold slope in thin-film SOI MOSFETs

The subthreshold conduction regime in thick- and thin-film SOI MOSFETs is studied. Using the depletion approximation, a one-dimensional analytical expression for the subthreshold slope is derived, and equivalence with a simple capacitive network is proven. The model accounts for the influence of the back interface properties on the subthreshold swing in the thin-film regime. The coupling between front and back surface potential and the influence of the backside conduction on the front interface characteristics are accounted for. The case of double gate control is studied in more detail. Experimental verification of the model with measured subthreshold slopes in thin-form MOSFET devices is given     

Linear dynamic self-heating in SOI MOSFETs

A model for small-signal dynamic self-heating is derived for the general case of a two-port device and then specialized to the case of an SOI MOSFET. The model is fitted to measured data for an SOI MOSFET and shown to accurately describe the frequency dependence of the self-heating. For this device, three time constants of 0.25 μs, 17 ns, and 90 ps adequately characterize the thermal response, showing that self-heating effects are active over a very wide frequency range     

Measurement of substrate current in SOI MOSFETs

A new “Quasi-SOI” MOSFET structure is shown to allow direct measurement of substrate current in a fully-depleted SOI device. The holes generated by impact ionization near the drain are collected at the substrate terminal after they have traversed the source-body barrier and caused bipolar multiplication. By monitoring this hole current, direct characterization of the impact-ionization multiplication factor, M, and the parasitic bipolar gain, β, was performed. It was found that M-1 increases exponentially with V_DS and decreases with V_GS, exhibiting a drain field dependence. The bipolar gain β was found to be as high as 1000 for V_GS-V_T=0 V and V_DS=-2.5 V, but decreases exponentially as V_DS increases. Finally, it was found that β also decreases as V_GS increases     

Comparative analysis of SOI and GOI MOSFETs

In this paper, the authors use a full-band particle-based simulator based on the cellular Monte Carlo method to investigate and compare the performance of silicon-on-insulator (SOI) and germanium-on-insulator (GOI) technologies. To this end, p-type GOI and SOI MOSFETs of effective gate lengths ranging from 30 to 110 nm are simulated, and their static and dynamic characteristics are analyzed through simulations. The transconductance, channel conductance, current-voltage (I-V) characteristics, and cutoff frequencies are extracted from the simulation results. The results indicate that drive currents are enhanced up to 25% by replacing Si with Ge. The enhancement is not as significant with respect to the unity gain frequency, which is only increased by 13% in the case of a 50-nm MOSFET. Additionally, the I-V characteristics indicate that GOI MOSFETs are more sensitive to impact ionization than their SOI counterparts, and that the channel conductance is degraded.     

Body effect in tri- and pi-gate SOI MOSFETs

A simple model based on the representation of capacitive coupling effects between the front- and back-gate and the channels, has been developed for tri-gate and pi-gate SOI MOSFETs. The model has been validated using numerical simulation of the body factor in such devices, as well as by experimental results. The body factor is much smaller than in regular, single-gate silicon-on-insulator devices because of the enhanced coupling between gate and channel and because the lateral gates shield the device from the electrostatic field from the back gate.     

Room-Temperature Low-Dimensional Effects in Pi-Gate SOI MOSFETs

Evidence of a one-dimensional subband formation is found in Pi-gate SOI MOSFETs at room temperature as oscillations are found in the$I_D(V_G)$characteristics. These oscillations correspond to an intersubband scattering. Even though the height-to-width ratio of the silicon fins is equal to five, the device behavior is better described by a one-dimensional semiconductor theory than by a two-dimensional gas model.