静态存储器保持状态下几种不同漏电流压制技术的漏电流拆分式分析

SRAM standby leakage reduction plays a pivotal role in minimizing the power consumption of application processors.Generally,four kinds of techniques are often utilized for SRAM standby leakage reduction: V_dd lowering（VDDL）,V_ss rising（VSSR）,BL floating（BLF） and reversing body bias（RBB）.In this paper,we comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage.It is disclosed that the performance of these techniques depends on the leakage composition of the SRAM cell and temperature.This has been verified on a 65 nm SRAM test macro.     

Stability and leakage characteristics of novel conducting PMOS based 8T SRAM cell

The stability and leakage power of SRAMs have become an important issue with scaling of CMOS technology. This article reports a novel 8-transistor (8T) SRAM cell improving the read and write stability of data storage elements and reducing the leakage current in idle mode. In read operation, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In write operation, a negative bias on the cell facilitates to change contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates 2× higher read stability while bearing 20% better write-ability at 1.2 V typical condition and a reduction by 45% in leakage power consumption compared to the standard 6T cell. Results of the bit-cell architecture were also compared to the dual-port 8T SRAM cell. The stability enhancement and leakage power reduction provided with the proposed cell are confirmed under process, voltage and temperature variations.     

一种低压低功耗SRAM/SOI单元设计

提出一种改进4管自体偏压结构SRAM/SOI单元.基于TSUPREM4和MEDICI软件的模拟和结构性能的分析,设计单元结构并选取结构参数.该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOSSRAM单元中的pMOS元件,具有面积小、工艺简单的优点.该结构可以在0.5V的电源电压下正常工作,与6管单元相比,该单元瞬态响应正常,功耗只有6管单元的1/10,满足低压低功耗的要求.     

A Low Power SRAM/SOI Memory Cell Design

提出一种改进4管自体偏压结构SRAM/SOI单元. 基于TSUPREM4和MEDICI软件的模拟和结构性能的分析，设计单元结构并选取结构参数. 该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOS SRAM单元中的pMOS元件，具有面积小、工艺简单的优点. 该结构可以在0.5V的电源电压下正常工作，与6管单元相比，该单元瞬态响应正常，功耗只有6管单元的1/10，满足低压低功耗的要求.     

低功耗容软错误的65 nm CMOS 12管SRAM单元

提出了一种具有软错误自恢复能力的12管SRAM单元。该单元省去了专用的存取管,具有高鲁棒性、低功耗的优点。在65 nm CMOS工艺下,该结构能够完全容忍单点翻转,容忍双点翻转的比例是64.29%,与DICE加固单元相比,双点翻转率降低了30.96%。与DICE、Quatro等相关SRAM加固单元相比,该SRAM单元的读操作电流平均下降了77.91%,动态功耗平均下降了60.21%,静态电流平均下降了44.60%,亚阈值泄漏电流平均下降了27.49%,适用于低功耗场合。     

SRAM 6T存储单元电路的PSPICE辅助设计

首先从双稳态电路入手,分析了SRAM 6T单元电路的工作原理和设计要求。基于实际工艺下MOS晶体管的SPICE模型,给出了一组可行的设计参数。用PSPICE对设计出的6T存储单元进行了功能验证。     

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations.     

6T SRAM cell analysis for DRV and read stability

The present paper analyzes the hold and read stability with temperature and aspect ratio variations. To reduce the power dissipation, one of the effective techniques is the supply voltage reduction. At this reduced supply voltage the data must be stable. So, the minimum voltage should be discovered which can also retain the data. This voltage is the data retention voltage(DRV). The DRV for 6T SRAM cell is estimated and analyzed in this paper. The sensitivity analysis is performed for the DRV variation with the variation in the temperature and aspect ratio of the pull up and pull down transistors. Cadence Virtuoso is used for DRV analysis using 45 nm GPDK technology files. After this, the read stability analysis of 6T SRAM cell in terms of SRRV(supply read retention voltage) and WRRV(wordline read retention voltage) is carried out. Read stability in terms of RSNM can be discovered by accessing the internal storage nodes. But in the case of dense SRAM arrays instead of using internal storage nodes, the stability can be discovered by using direct bit line measurements with the help of SRRV and WRRV. SRRV is used to find the minimum supply voltage for which data can be retained during a read operation. Similarly, WRRV is used to find the boosted value of wordline voltage, for which data can be retained during read operation. The SRRV and WRRV values are then analyzed for different Cell Ratios. The results of SRRV and WRRV are then compared with the reported data for the validation of the accuracy of the results.     

Secondary side post regulator for improving cross regulation and reducing standby power consumption

The quest for improved energy savings is driving research into power converter high-efficiency operation under extremely light-load conditions. The use of multiple output converters to satisfy circuit needs and cost requirements adds additional complication to the standby mode power-consumption problem. This is due to the difficulty of satisfying both good cross-regulation under various load conditions as well as high efficiency in the standby mode simultaneously; because topologies that exhibit a good cross-regulation performance, such as resonant converters, generally have a poor efficiency problem under extremely light-loads. A secondary side post regulator (SSPR) is proposed to reduce the standby power consumption and to improve the cross-regulation performance of single- controller multiple-output channel power converters. It is capable of reducing the power consumption of the power converter as well as the SSPR. The SSPR is analysed using its operational principles and small signal models. A 110?W experimental prototype was built to verify the standby power consumption and cross-regulation performance using the proposed SSPR.     

A new low-power 10T SRAM cell with improved read SNM

This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM).     

一种能够降低空调待机功耗的电源控制电路

为了有效降低空调的待机功耗,设计了一种旨在降低空调待机功耗的电源控制电路。该控制电路通过取样电路检测空调实际工作电流的大小,判断空调的工作状态,当检测到空调处于待机状态超过1min左右,控制电路自动切断空调插座的电源。实测证明该控制电路可以有效降低空调的待机功耗,可以做到待机功耗不大于1w。该控制电路采用光耦可控硅作为核心控制元件,控制电路中使用了红外接收器,其正常工作时不会影响空调遥控器的正常使用。     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

一种低功耗无电容型LDO的设计

提出了一种片上集成的低功耗无电容型LDO(low drop out)电路。该电路采用折叠型cascode运放作为误差放大器,通过消除零点的密勒补偿技术提高了环路稳定性;并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进行保护。此外,在电路中加入了省电模式,可在保持LDO输出1.8 V情况下节省大于70%的功耗。该设计采用HHNEC 0.13μmCMOS工艺,仿真结果显示:在2.5~5.5 V电源供电、各个工艺角及温度变化条件下,LDO输出的线性调整率小于2.3 mV/V,负载调整率小于14μV/mA,温度系数小于27×10-6/℃;在正常工作模式下,整个LDO消耗85μA电流;在省电模式下仅消耗23μA电流。     

多模式开关电源控制芯片的低功耗设计

针对降低多模式开关电源控制芯片在轻载与待机工作模式下功耗,提高其全负载条件下工作效率的需要,提出一种开关电源控制芯片供电系统的设计方案,实现了其在启动、关断、重载、轻载以及待机等各种工作情况下的高效率低功耗工作。该供电系统主要包括欠压锁定电路、数字模块电源单元和两种不同的模拟模块电源单元,以及状态检测模块和模式控制逻辑单元,能够实现电源的上电、掉电控制,同时能够根据电源的负载条件控制各模块的开通关断以实现低功耗工作。该系统已应用于绿色多模式反激式开关控制器的设计中,取得了提高电源效率、降低待机功耗的作用。芯片采用1.5μm BiCMOS工艺设计制成。测试表明,所设计电源的各项指标均已达到设计要求。     

28 nm低功耗工艺SRAM失效分析

在28 nm低功耗工艺平台开发过程中,对1.26 V测试条件下出现的SRAM双比特失效问题进行了电性能失效模式分析及物性平面和物性断面分析.指出失效比特右侧位线接触孔底部空洞为SRAM制程上的缺陷所导致.并通过元素成分分析确定接触孔底部钨(W)的缺失,接触孔底部外围粘结阻挡层的氮化钛(TiN)填充完整.结合SRAM写操作的原理从电阻分压的机理上解释了较高压下双比特失效,1.05 V常压下单比特不稳定失效,0.84 V低电压下失效比特却通过测试的原因.1.26 V电压下容易发生的双比特失效是一种很特殊的SRAM失效,其分析过程及结论在集成电路制造行业尤其是对先进工艺制程研发过程具有较好的参考价值.     

Memristive SRAM cell of seven transistors and one memristor

In this work, a novel memristive SRAM cell is designed using seven transistors and one memristor (7T1M). In this 7T1M SRAM cell, the non-volatile functionality is achieved by adding a single memristor and a transistor to the design of a volatile SRAM cell. The designing of the 7T1M SRAM cell also introduces VCTRL which allows bidirectional current flowing through the memristor, instead of relying on complementary input sources which would require more design components. In this article, memristive SRAM cells available from the literature are simulated using the same simulation environment for a fair comparison. Simulations show that the 7T1M SRAM cell has the least power consumption against other memristive SRAM cells in the literature. The 7T1M SRAM cell operates with an average switching speed of 176.21 ns and an average power consumption of 2.9665 μW. The 7T1M SRAM cell has an energy-delay-area product value of 1.61, which is the lowest among the memristive SRAM cells available in the literature.     

超深亚微米无负载四管与六管SRAM SNM的对比研究

采用基于物理的α指数MOSFET模型与低功耗传输域MOSFET模型，推导了新的超深亚微米无负载四管与六管SRAM存储单元静态噪声容限的解析模型．对比分析了由沟道掺杂原子本征涨落引起的相邻MOSFET的阈值电压失配对无负载四管和六管SRAM单元静态噪声容限的影响。     

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

A novel nine transistor (9T) CMOS SRAM cell design at 32 nm feature size is presented to improve the stability, power dissipation, and delay of the conventional SRAM cell along with detailed comparisons with other designs. An optimal transistor sizing is established for the proposed 9T SRAM cell by considering stability, energy consumption, and write-ability. As a complementary hardware solution at array-level, a novel write bitline balancing technique is proposed to reduce the leakage current. By optimizing its size and employing the proposed write circuit technique, 33% power dissipation saving is achieved in memory array operation compared with the conventional 6T SRAM based design. A new metric that comprehensively captures all of these figures of merit (and denoted to as SPR) is also proposed; under this metric, the proposed 9T SRAM cell is shown to be superior to all other cell configurations found in the technical literatures. The impact of the process variations on the cell design is investigated in detail. HSPICE simulation shows that the 9T SRAM cell demonstrates an excellent tolerance to process variations comparing with the conventional SRAM cells.     

130nm工艺极低泄漏电流亚阈值SRAM存储单元设计

本文提出一款工作在亚阈值（200 mV）区域且具有极低泄漏电流的亚阈值SRAM存储单元。该存储单元采用自适应泄漏电流切断机制,该机制在没有带来额外的动态功耗和性能损失的前提下,同时降低动态操作（读/写操作）和静态操作时的泄漏电流。差分读出方式和可配置操作模式的应用,使得本文设计在亚阈值条件下（200 mV）仍然保持足够的鲁棒性。仿真结果表明,相比于参考文献中的亚阈值存储单元本文设计具有：（1）在不同的工艺角下,均具有较大的读噪声容限和保持噪声容限;（2）在动态操作和静态操作时均具有极低的泄漏电流。最后,我们将该存储单元成功的应用于IBM 130nm工艺下的一款 bits存储阵列中,测试结果表明该存储阵列可以在200 mV电源电压条件下正常工作,所对应功耗（包括动态功耗和静态功耗）仅0.13 μW,是常规六管存储单元功耗的1.16%。