New two-CFOA-based floating immittance simulators

This paper presents new topologies for emulating floating immittance functions using three to five passive elements and only two current-feedback operational-amplifiers (CFOAs). The feasibility of using only two CFOAs and two passive components is explored. The proposed topologies can emulate lossy positive and negative inductances and capacitance-, inductance-, resistance-multipliers, and frequency dependent negative and positive conductances. The functionality of the proposed circuits was experimentally verified using the commercially available AD844 CFOA. The experimental results are in excellent agreement with theoretical calculations.     

CMOS four terminal floating nullor design using a simple approach

In this study a simple approach for design of four terminal floating nullor (FTFN) is introduced and two new CMOS FTFN topologies are proposed using the approach from suitable CMOS negative current conveyor (CCII−) structures. The performance of the proposed circuits was tested by computer simulation program. The feasibility of the proposed circuits was shown on a current-mode band-pass filter example constructed using one of the proposed CMOS FTFN circuits. The simulation results are given to confirm the predicted theory.     

Low-Voltage Current Feedback Operational Amplifiers

A number of current feedback operational amplifier topologies suitable for operation in a low-voltage environment are introduced in this paper. Their realization is based on the corresponding low-voltage second generation current conveyor topologies. Important performance factors such as accuracy, bandwidth, and linearity have been considered, and the obtained simulation results have been compared in order to evaluate the behavior of the proposed topologies.     

Very Low Voltage CMOS Current Multiplier with Floating DC Level Shifters

A compact, wide dynamic range, four-quadrant analog CMOS current multiplier is presented. The use of floating DC level shifters (floating batteries) made by resistors and current sources allows low supply voltages while maintaining at the same time a large input range and low harmonic distortion. Measurement results for an experimental prototype in a 0.8 m CMOS technology demonstrate on silicon the proposed technique.     

Novel Architectures of Class AB CMOS Mirrors with Programmable Gain

Two schemes for power-efficient gain-programmable V-I conversion based on class AB CMOS mirrors are introduced. The proposed topologies also allow for high-speed gain-programmable precision rectification. Experimental results from a test chip prototype in 0.5- m CMOS technology with ±1 V supplies are shown that validate the proposed circuits.     

Novel grounded parallel inductance simulators realization using a minimum number of active and passive components

In this paper novel lossless and lossy grounded parallel inductance simulators are reported. All grounded inductor simulator circuits employing only a single DXCCII and three passive components are proposed. The proposed topologies realized all grounded parallel inductance variations. To demonstrate the performance of the presented DXCCII based parallel inductance simulators, we used one of the circuits to construct a third order high-pass filter, a voltage-mode band-pass filter and LC oscillator. Simulation results are given to confirm the theoretical analysis. The proposed DXCCII and its applications are simulated using CMOS 0.35 μm technology.     

Class of floating, generalised, positive/negative immittanceconvertors/inverters realised with operational mirrored amplifiers

Through a systematic formulation based on nullors, a class of eight generalised positive/negative floating impedance (FI) configurations, realisable with four operational mirrored amplifiers (OMAs) and only three passive elements, is derived. The advantages offered by the proposed configurations are not simultaneously available in any of the previously known FI configurations employing opamps, current conveyors or OMAs. The feasibility of the new formulations together with some of their applications, have been confirmed by SPICE simulations     

Low-Voltage Rail-to-Rail Tunable FGMOS Transconductor

A compact, tunable CMOS transconductor is presented. The combined use of a Floating-Gate MOS (FGMOS) differential pair and a floating DC level shifter allows the use of low supply volatages while maintaining at the same time a rail-to-rail input range, low distortion and high linearity. Measurement results for a prototype fabricated using a 0.8 m CMOS technology are provided, confirming on silicon the validity of the proposed approach.     

Full binary combination schema for floating voltage source multilevel inverters

This paper presents schema of operation for floating voltage source multilevel inverters. The primary advantage of the proposed schema is that the number of voltage levels (and thus power quality) can be increased for a given number of semiconductor devices when compared to the conventional "flying capacitor" topology. However, the new schema requires fixed floating sources instead of capacitors and therefore is more suitable for battery power applications such as electric vehicles, flexible AC transmission systems and submarine propulsion. Alternatively transformer/rectifier circuits may be used to supply the floating sources in a similar way to cascaded H-bridge inverters. Computer simulation results are presented for 4-level, 8-level, and 16-level inverter topologies. A 4-level laboratory test verifies the proposed method.     

A systematic realization of current mode universal biquad filters

A family of current mode universal biquads has been proposed. The biquad filters employ multiple output floating nullor (MOFN) configured as multiple output current conveyors (MOCC). The five-MOFN-based biquad has the property of independently tunable gain, bandwidth, and cut-off frequency without having any passive component matching constraint. Although the four/three MOFN-based universal biquads offer limited tunability of different parameters they do not have any parameter matching constraint on them and in addition, they offer the advantage of reduction in the number of MOFNs and resistances. The workability of all the proposed circuits has been verified using PSPICE simulations based CMOS MOFNs implemented in 0.35?µ CMOS technology.     

Differential voltage current controlled current conveyor with low-voltage operation capability

A novel differential voltage current controlled current conveyor topology is introduced in this article. It has the capability for operating in a low-voltage power supply environment and, also, offers resistorless filter realisations. The main attractive offered benefit is that the handling of AC signals is exclusively performed by nMOS transistors and, thus, the proposed element has capability for high-frequency operation. The performance of the proposed cell has been experimentally verified through the realisation of two 3rd-order filters, derived according to the leapfrog and component substitution methods. The filter topologies have been fabricated through the AMS 0.35 µm CMOS process.     

Switched-current (SI) integrators with reduced effect of transistor mismatches

Switched-current (SI) circuits are widely used for analog sampled-data signal processing, due to their compatibility to the pure digital CMOS process. As their main building blocks are current mirrors, they suffer from the effects of MOS transistor parameters mismatch. In this paper, the Functional Block Diagram (FBD) of already known integrator circuits is modified in such a way that the number of required current mirrors is reduced. Thus, the behavior of the derived integrator topologies, with respect to the effect of MOS transistor parameters mismatch, is improved.A comparison is performed, concerning the performance of the proposed bilinear integrator circuits and those that are already introduced in the literature. For this purpose, a fifth-order Chebyshev lowpass SI filter transfer function was simulated. In the case of the proposed filter configurations, the obtained results show that their performance is improved in terms of the effects of MOS transistor parameters mismatch, DC power dissipation, and total required silicon area.     

A simple method for determination of Fowler–Nordheim tunnelling parameters

A simple technique for extracting the Fowler–Nordheim (FN) tunnelling parameters is proposed. It consists of measuring the Drain-Source current of a floating gate transistor while a linear ramp voltage is applied to a simple injector structure attached to the transistor's floating gate. Such a test device is fabricated using a standard CMOS process. The parameters obtained can be used in a freely available electrical simulator as SPICE3f5 (NGSPICE), but in general it can be easily adapted to other SPICE-like programs. We describe the technique step-by-step and a comparison is made of simulated and measured FN tunnelling parameters, for a floating gate transistor with tunnelling injectors. A good agreement has been found between experimental and simulated data.     

一种基于交错自举控制技术的全集成SCPC浮动电压驱动电路

设计了一种适用于全集成开关电容功率转换器(SCPC)的浮动电压驱动电路。该电路采用交错自举控制技术,周期性地利用多相交错SCPC中的特定单元为其他单元提供自举驱动。该电路实现了全部功率开关的浮动电压驱动,并且适用于所有SCPC拓扑。相比于传统浮动电压驱动方案,该驱动电路的硬件开销与SCPC中的器件数目无关。提出的浮动电压驱动电路应用于一个8相可重构SCPC中,仿真结果证明了其功能的正确性。     

Floating Immittance Function Simulator and Its Applications

A new floating immittance function simulator circuit is proposed using two different active elements, a dual-output second generation current conveyor (DO-CCII) and an operational transconductance amplifier (OTA). The presented circuit can realize a positive and negative floating inductor, capacitor and resistor depending on the passive component selection. Since the passive elements are all grounded, this circuit is suitable for fully integrated circuit design. The circuit does not require any component matching conditions, and it has a good sensitivity performance with respect to tracking errors. Moreover, the proposed positive and negative inductance, capacitor and resistor simulator can be tuned electronically by changing the biasing current of the OTA or can be controlled through the grounded resistor or capacitor. The proposed floating inductor simulator circuit is demonstrated by using a SPICE simulation for 0.35 μm TSMC CMOS technology. The proposed circuit consumes an average power of 1 mW using ±1.5 V supply voltages.     

Universal filters of arbitrary order and type employing square-root-domain technique

Novel Single Input Multiple Output (SIMO) and Multiple Input Single Output (MISO) universal filter topologies of arbitrary order and type are introduced in this paper. The proposed topologies have been realised by employing Square-Root Domain (SRD) technique. An offered benefit of the universal filter topologies is that only grounded capacitors are required for their implementations and the resonant frequency of the filters can be electronically controlled by an appropriate dc current. The proposed universal filters simultaneously offer all the five standard filtering functions i.e. Lowpass (LP), Highpass (HP) and Bandpass (BP), Bandstop (BS) and Allpass (AP) frequency responses. In addition, the SIMO topology is generic in the sense that it can yield four different stable filter configurations. Two design examples are provided in each configuration and the correct operation of the corresponding topologies has been evaluated through the PSPICE software with BSIM 0.35-µm CMOS process model parameters.     

Realization of New Mutually Coupled Circuit Using CC-CBTAs

A novel circuit for the realization of the mutually coupled circuit using three current-controlled current backward transconductance amplifiers (CC-CBTAs) as active components is proposed. The active mutually coupled circuit structures are also called the synthetic transformers. The circuit is derived by using three floating simulated inductors that are connected as the T-type transformer model. The circuit has the following attractive advantages: (i) The values of a primary self-inductance, a secondary self-inductance and a mutual inductance can be independently tuned by the transconductance gain of the CC-CBTAs; (ii) The circuit uses three grounded capacitors that are suitable from the point of integrated circuit implementation; (iii) It uses only three active components; (iv) It has a good sensitivity performance with respect to the tracking errors; (v) Both positive and negative couplings are achieved and the coupling coefficient is not limited by 1 in magnitude; (vi) Symmetrical coupling is achieved without necessitating any matching condition; (vii) The proposed circuit has a floating structure.     

FDCCII-based FDNR simulator topologies

In this article, three new circuits for realising frequency-dependent negative resistance (FDNR) are proposed. All proposed circuits employ a single fully differential current conveyor, grounded capacitors and resistor. Proposed circuits consist of minimum number of passive and active elements. All proposed circuits are lossless FDNR. The performance of the proposed FDNR is demonstrated on the third-order Butterworth low-pass filter. Simulation results are included to verify the theory.     

Design of Two‐Stage Class AB CMOS Buffers: A Systematic Approach

A systematic approach for the design of two‐stage class AB CMOS unity‐gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity‐gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 µm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 µW).     

A Study of Different Class AB Log Domain First Order Filters

Several different class AB log-domain/translinear filters are compared in terms of their noise and distortion behavior using both analytical and simulation results. A few of the circuit topologies shown have not been considered before and are derived using a new theory for class AB dynamical circuits recently proposed. The study, although approximate, suggests ways in which both noise and distortion performance may be optimized by appropriate choice of circuit topology. Other practical aspects of the designs are also discussed.