Effect of wafer thinning methods towards fracture strength and topography of silicon die

This paper characterizes die damage resulting from various wafer thinning processes. Die fracture strength is measured using ball breaker test with respect to die surface finish. Further study on surface roughness and topography of each surface finish is obtained by atomic force microscopy (AFM) and scanning electron microscopy (SEM) techniques. Stress relief process with 25 μm removal is able to strengthen 100 μm wafer by 20.4% using chemical wet etch and 75 μm wafer by 36.4% with plasma etch. Relatively, plasma etching shows higher fracture strength and flexibility compared to chemical wet etch. This is due to topography of the finished surface of plasma etch is smoother and rounded, leading to a reduced stress concentration, hence improved fracture strength.     

Evaluation of different oxidation methods for silicon for scanning capacitance microscopy

Different oxides, namely, native, thermal, and wet-chemical (H₂SO₄+H₂O₂ based) oxides on Si are evaluated in the context of scanning capacitance microscopy (SCM). The samples investigated consisted of uniformly doped Si substrates and p-type epitaxial doping-staircase structures with concentrations ranging from 5×10¹⁴ to 2×10¹⁹ cm⁻³. The bias for which the SCM signal (dC/dV) is maximised for the lowest doped region was used for comparing the different oxidation methods. It is shown that for a better evaluation of the surface oxide properties, it is essential to obtain dC/dV curves for a sufficiently large doping range. Best results in terms of low values of flat-band voltages (1 V), uniformity, and consistency across a large doping range were obtained for the wet-chemical oxide. For the native oxide case, the difference in the dC/dV peak bias values obtained at regions doped to 5×10¹⁴ to 10¹⁷ cm⁻³ was anomalously large and suggests appreciable distortion of the dC/dV curves. For the same oxidation procedure the full-width at half-maximum of the dC/dV curve obtained on the cleaved surface is typically 2 times larger than that on the planar (1 0 0) surface. It is most likely that interface states are responsible for the observed distortion.     

Whisker test methods of JEITA whisker growth mechanism for test methods

As the industry moves toward lead-free electronics, a replacement for the traditional tin-lead plating is required. Pure tin is the coating of choice for many suppliers, but there is a well-known problem with the growth of tin whiskers. A whisker is comprised of a tin crystal which, after an incubation period, grows with time. Whiskers may grow long enough to cause shorts in electronic circuits. A test method is required for evaluating the reliability risk inherent in tin whiskers. The Japanese government requested the Japan Electronics and Information Technology Industries Association (JEITA) to establish test methods for solderability, reliability, whisker, and migration for lead-free electronics. The goal of this subcommittee was to propose the test methods for tin whiskers by March 2004. The committee carried out a literature survey, and developed hypotheses for whisker growth, which was then applied to test methods. Two types of studies were undertaken. One is a fundamental study to verify the hypothesis. The other looked at accelerated tests to develop recommended test conditions. As a result, we found that the diffusion of copper, oxidation, and thermal cycling all influence tin whisker growth. This paper describes the results of the fundamental studies and reports on the JEITA whisker growth mechanism.     

A three-parameter Weibull-like fitting function for flip-chip die strength data

Die cracking in the assembly and reliability testing of flip-chip (FC) packages is often a major concern. A widely used die strength test is the so-called the four-point bending (4PB) test. In the 4PB test, the die is under pure bending and the strength of the die is determined by its breaking tensile stress. Although the 4PB test has been widely used, a well-established relation between the 4PB result and the die breaking in FC package has not been reported. This paper discusses the relation from a probabilistic mechanics point of view. The theory considers the following issues in the material strength test and the application loading conditions: (1) the die top in the 4PB test is under uniaxial tensile stress and the die in FC package is under multi-axial stress; (2) the 4PB test only puts part of the die top under tension and the die top in FC plastic package has almost 100% of the die top area under tension; (3) the die stress in the 4PB and in the package has a different distributions which contribute differently to die cracking. Weibull distribution will be used to analysis the 4PB test data. A three-parameter Weibull distribution fitting procedure will be presented. The function form of the cumulative density function of Weibull distribution is specially modified to take the above three issues into consideration and reflect the stress distribution difference between the test and application. The three-parameter Weibull fitting is compared to a two-parameter fitting. It turns out that some systems need three-parameter fitting and some other systems only need the two-parameter fitting. For systems need three-parameter fitting, a two-parameter fitting will be too conservative in design.     

Effect of deposition methods on dielectric breakdown strength of PECVD low-k carbon doped silicon dioxide dielectric thin films

The effect of deposition methods on dielectric breakdown strength of PECVD low-k dielectric carbon doped silicon dioxide films is investigated. I-V measurements were performed using metal-insulator semiconductor structures for carbon doped silicon dioxide thin films with various thicknesses by single deposition station and six sequential deposition systems. I-t measurements are also performed for films with the thickness of 32 nm prepared using both deposition methods. Comparison studies have been carried out for the thickness dependence, temperature dependence, conduction mechanism and time dependence of dielectric breakdown for carbon doped silicon dioxide with single layer and six sub-layers. Results demonstrated that both films follow the newly obtained relationship between dielectric strength E_B and thickness d, i.e. E_B∝(d−d_c)⁻ⁿ, but with a lower exponential factor n and a larger thickness limit d_c for films with six sub-layers. It is also demonstrated that films with six sub-layers have a higher dielectric strength in all the thickness and temperature ranges, a thickness independent thermal behavior and a longer lifetime under constant voltage stressing. This indicates that by tuning the deposition methods smaller thickness with desired dielectric properties can be achieved.     

Novel RF process monitoring test structure for silicon devices

This paper demonstrates a novel RFCMOS process monitoring test structure. Outstanding agreement in dc and radio frequency (RF) characteristics has been observed between conventional test structure and the new process monitoring test structure for MOSFET with good correlations in measured capacitances also noted for metal-insulator-metal capacitor and MOS varactor. Possible process monitoring test structure is also suggested as a reference benchmarking indicator for interconnects.     

MEMS薄膜断裂强度测试结构

多晶硅断裂强度是MEMS器件极限工作的主要参数,也是MEMSCAD数据库建立的重要方面之一,在微小尺寸的情况下断裂强度的测试方法与大尺寸时有很大的不同,测试结果会受到很多因素的影响。本文总结了近几年MEMS薄膜断裂强度的测试方法及存在的问题,对进一步结构设计有一定的参考价值。     

Evaluation of lateral diffusion factor in silicon from subthresholdcurrent in short-channel vertical SIT test structure

A measurement method for the evaluation of the lateral diffusion factor of deep implanted regions in lightly doped material is proposed. The method is based on measurements of the subthreshold current versus drain voltage in vertical static induction transistor (SIT) devices. The subthreshold current is very sensitive to SIT channel width and hence to lateral diffusion of the gate regions, as shown by two-dimensional numerical analysis. Experimental results obtained for test structures fabricated with different boron doses and the same drive-in treatment indicate a lateral diffusion factor of 64% for a typical drive-in process     

Reliability test methods for media-compatible pressure sensors

Two applications of media exposure testing of pressure sensors with barrier coatings are presented. Experimentation was performed on an apparatus that was developed specifically for the exposure of these devices with in situ output voltage measurement in organic or aqueous environments. The first example illustrates the swelling of fluorosilicone gels in fuels and establishes a solubility parameter for one fluorosilicone gel between 6-8 (cal/cm³)^1/2. While exposure to organic solutions has not been observed to cause catastrophic failure of fluorosilicone-gel-filled devices, corrosion is accelerated in subsequent aqueous solution exposure. An additional experiment was used to simulate automotive exhaust gases and water by exposing devices to a fuel mixture followed by an acidic solution. The second experiment was performed to study corrosion under parylene coatings during exposure to an alkaline test solution for white-goods applications. Acceleration factor expressions have been estimated considering parylene coating thickness, solution pH, and applied device supply voltage as acceleration means. These expressions have been used to evaluate parylene-coated pressure sensors against a benchmark lifetime requirement. For a 1% failure rate, parylene-coated pressure sensors survived approximately 500 h, whereas an alternative, fluorosilicone gel over parylene C coating survived over 2000 h. Furthermore, these media exposure experiments provided insight into the failure mechanisms and defined acceleration factors     

The maximum dielectric strength of thin silicon oxide films

Thin film silicon oxide capacitors with nonshorting breakdowns were investigated. Breakdowns appear in three forms: single hole, self-propagating, and maximum voltage breakdowns. Single hole and self-propagating breakdowns occur at flaws, and self-propagating breakdowns develop only when the resistor to the source is relatively small, less than 10 kΩ in these experiments. After flaws are burned out by single hole breakdowns, with larger source resistors the maximum voltage breakdown can be observed, destroying the whole capacitor simultaneously. Plotting current against voltage, the current increase is quasi-exponential, but prior to maximum voltage breakdown, the current continues to increase while the voltage decreases slightly below a maximum value Vm. Assuming thermal instability as the cause for this change in the I-V relationship, we have derived an expression for the maximum voltage Vm. Calculated results for fields up to 9.5 MV/cm were found to agree well with measurements for temperatures from -145°C to 65°C and for thicknesses from 3000 Å to 50 000 Å. Fmdecreases with increasing temperature and thickness of insulation, and is higher for silicon dioxide than for silicon monoxide films. Maximum voltage breakdown occurs when the quasi-exponential increase of leakage current with field produces thermal instability over the whole capacitor area. The maximum dielectric strength is characteristic of the whole capacitor and is determined by its electrical and thermal conductance.     

An overview of experimental methodologies and their applications for die strength measurement

As the trends in semiconductor packages continue toward a decrease in overall package size and an increase in functionality and performance requirements, they bring challenges of processing, handling, and understanding smaller components and, in particular, thinner dies. In the meantime, high reliability remains a critical necessity. It is necessary to be able to appropriately characterize thinned dies in terms of their mechanical integrity and, equally important, in terms of the processes used to produce them. In practice, die strength can be adversely affected during various manufacturing processes, such as thinning and singulation. A realistic understanding of the significance of processing on die strength is gained through the study of the actual, processed component. This work outlines three methodologies that enable the measurement of die strength and demonstrates their application in three studies. Characterization of die damage, experimentation, and failure analysis are coupled to gain understanding of die strength with respect to processing conditions. The approaches demonstrated ultimately show the use of such information toward quantifying die strength, developing design criteria, selecting wafer processes, and optimizing processes.     

碳化硅功率器件结温提取方法研究综述

碳化硅材料由于其独特优势受到了广泛的重视。适用于硅器件的一些传统结温提取方法,在碳化硅器件中应用将会失效。因此,需要找到适用于碳化硅器件的结温提取方法。本文介绍了碳化硅的材料特性及其在功率器件中的应用。对结温提取的传统方法和新兴方法进行了归纳总结和比较分析。总结了功率半导体器件常用的热敏参数,介绍了各参数在碳化硅中的应用现状。     

Fracture strength characterization and failure analysis of silicon dies

This paper characterizes fracture strength of a silicon die as a first step to predict and prevent die cracking during package assembly, reliability tests, and operation life. Die strength is measured via the three-point bend test conducted using a micro-force tester. Strength reduction due to surface defects, such as tiny notches or micro-cracks that are introduced through wafer backside grinding is evaluated. It is observed that die strength strongly depends on the grinding patterns, i.e. minimum die strength in a wafer is found if the grinding mark is in parallel with the loading axis. Furthermore, fracture strength of dies with different wafer surface conditions like polishing and no treatment (grinding) are also examined. Polished wafers possess the highest silicon strength owing to its minimum surface flaws. On the other hand, untreated wafers contain the most severe surface defects; hence exhibit the lowest die strength. Geometrical factors (square vs. rectangular) and die thickness (4 vs. 6 mils) are probed as well, however these factors do not contribute to die strength degradation. Surface morphology and roughness studies of silicon dies via scanning electron microscope and atomic force microscope also confirmed that die strength degradation is mainly controlled by surface defect (roughness) levels. Observed fracture modes also correlate well with measured die strength.     

Wi-Fi产品抗干扰能力评估及测试方法分析

提出了一种定量评估Wi-Fi产品抗干扰能力的测试方法,通过对比干扰前与干扰后产品的吞吐量性能来评估产品实际的抗干扰能力.该方法能够直观的评估产品在各种RF干扰源存在的情况下所表现出来的性能差异,真实有效的反应产品的抗干扰能力.     

IC卡中薄芯片碎裂失效机理的研究

薄/超薄芯片的碎裂占据IC卡早期失效的一半以上,其失效模式、失效机理亟待深入研究.本文分析了芯片碎裂的失效模式和机理,并结合实际IC卡制造工艺以及IC卡失效分析实例,就硅片减薄、划片、顶针及卡片成型工艺对薄IC芯片碎裂的影响进行深入探讨.     

Formal methods for generating protocol conformance test sequences

The four major methods of conformance test generation reported in the literature are reviewed: transition tours; distinguishing sequences; characterizing sequences; and unique input/output sequences. These methods are used to test the control portion of a protocol specification. The conformance testing concepts developed in the standards world are summarized. Their relationship with the four formal methods is discussed     

单模光纤非线性系数n2/Aeff的测量方法

通信距离的延长和WDM通道数的增加使光纤非线性效应日益显著，如何准确地测量非线性系数的大小成了人们关注的问题，文章介绍了几种非线性系数的测量方法，并对它们的优缺点进行了较全面的分析和比较。     

天线远场调试测量方法

天线研制、生产过程中,天线调试是一项重要工作。本文将天线测试和调试进行了一体化研究。详细研究了天线测试系统、测试环境、天线调测方法等,给出了具体的天线远场调测系统,并经试验验证了所研究的天线远场调测方法的合理性与可行性。     

微电子封装界面强度的复合模式弯曲测试

设计了一种复合模式界面开裂测试装置,通过改变加载臂长来实现作用在试样裂纹尖端的不同应力模式。以试验测得的临界载荷及对应位移、裂纹扩展长度为条件,建立与测试装置对应的有限元模型,计算裂纹尖端模式角及在此模式角下的临界能量释放率。结果表明,装置所测试的模式角为7°～78°,以此为参数,可预测微电子封装界面强度。