共查询到20条相似文献,搜索用时 15 毫秒
1.
D. Guerrero M. J. Bellido J. Juan A. Millán P. Ruiz-De-Clavijo E. Ostua 《International Journal of Electronics》2013,100(12):819-842
In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches clocking scheme (PALACS) and four-phase parallel alternating latches clocking scheme (four-phase PALACS). In order to evaluate the timing performance, the authors introduce algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. From these waveforms it is possible to get parameters such as the non-overlapping time and the clock period. They have been implemented in a tool and have been used to compare the timing performance of the clocking schemes applied to a simple circuit. To analyse the power consumption the authors have electrically simulated a simple circuit for several operation frequencies. The most remarkable conclusion is that it is possible to save about 50% of the power consumption of the clock distribution network by using PALACS. 相似文献
2.
We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half VDD by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 μm CMOS technology, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation 相似文献
3.
Zhengtao Yu Xun Liu 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(11):1593-1601
Rotary clock is a resonant clocking technique that delivers on-chip clock signal distribution with very low power dissipation. Since it can only generate clock signals with multiple phases that are spatially distributed, rotary clock is often considered not applicable to industrial very large scale integration (VLSI) designs. This paper presents the first rotary-clock-based nontrivial digital circuit. Our design, a low-power and high-speed finite-impulse response (FIR) filter, is fully digital and generated using CMOS standard cells in 0.18 mum technology. We have shown that the proposed FIR filter is seamlessly integrated with the rotary clock technique. It uses the spatially distributed multiple clock phases of rotary clock and achieves high power savings. Simulation results demonstrate that our rotary-clock-based FIR filter can operate successfully at 610 MHz, providing a throughput of 39 Gb/s. In comparison with the conventional clock-tree-based design, our design achieves a 34.6% clocking power saving and a 12.8% overall circuit power saving. In addition, the peak current consumed by the rotary-clock-based filter is substantially lower by 40% on the average. Our study makes the crucial step toward the application of rotary clock technique to a broad range of VLSI designs. 相似文献
4.
This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it is insensitive to clock overlap. With the proposed interface circuit, both adiabatic and CMOS logic circuits are able to co-exist on a single chip, taking advantage of the strengths of each approach in the design of low power systems. 相似文献
5.
设计了一个与静态电路兼容的64位动态加法器,采用嵌入逻辑的动态触发器,以及多相位时钟技术,实现了与上、下级静态电路的接口.在加法器内部采用稀疏先行进位策略平衡逻辑路径长度以降低内部负载,提高性能.在STMicro90nmCMOS工艺下,该加法器可工作在4GHz时钟下,功耗45.9mW. 相似文献
6.
A rail-to-rail ping-pong op-amp achieves offset cancellation and 1/f noise reduction without folding of the input spectrum. The clocking scheme minimizes the clock feedthrough and the residual offset due to charge injection. With a clock frequency of 100 kHz, the residual offset is less than 100 μV, and the input referred noise is about 225 nV/Hz 1/2. The rail-to-rail distortion at 1 kHz is lower than -71 dB. The total silicon area is 610×420 μm2, and the circuit dissipates 1.5 mW from a single 5 V supply 相似文献
7.
A new CMOS four-quadrant switched current multiplier, operating from a single 3V power supply and employing two-phase clocking scheme, is proposed. The circuit is designed to perform one multiplication per clock cycle. SPICE simulations using 0.5 /spl mu/m CMOS process parameters have been carried out to verify the multiplier performance. 相似文献
8.
Woonghwan Ryu Wai A.L.C. Fan Wei Wai Lai Lai Joungho Kim 《Advanced Packaging, IEEE Transactions on》2002,25(1):18-27
Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution due to transmission line losses. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution,especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 μm TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node-board-level RF clock distribution networks is conducted using 3D full-wave EM simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers Lt; RO3003 high-frequency organic substrate 相似文献
9.
《Solid-State Circuits, IEEE Journal of》1972,7(1):92-93
A new approach to charge-coupled device (CCD) clocking has been developed that uses a single clock signal and dc bias on a device structure previously used for two-phase clocking. The one-phase approach results in improved operation by simplifying the clock circuit, reducing power consumption, and simplifying scanning of large CCD arrays. 相似文献
10.
A new power saving concept for boosted charge pumps is introduced, that combines two-step adiabatic switching, charge sharing and a simplified clocking scheme to double the power efficiency. Due to the charge charging the clock driver strengths can be reduced and therefore the peak value of the charging current is reduced by a factor of three. Further, the combination of tristate drivers and a new clocking scheme eliminates parasitic charge current peaks and together with the reduced current peaks the electromagnetic emission of the charge pump circuit is reduced significantly 相似文献
11.
Venkataraman G. Jiang Hu Liu F. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(2):149-158
The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have started playing an increasingly important role in limiting the performance of the clock network. Rotary clocking is a novel technique which employs unterminated rings formed by differential transmission lines to save power and reduce skew variability. Despite its appealing advantages, rotary clocking requires flip-flop locations to match predesigned clock skew on rotary clock rings. This requirement poses a difficult chicken-and-egg problem which prevents its wide application. In this paper, we propose an integrated placement and skew scheduling methodology to break this hurdle, making rotary clocking compatible with practical design flows. A network flow based flip-flop assignment algorithm and a cost-driven skew optimization algorithm are developed. We also present an integer linear programming formulation that minimizes maximum capacitance loaded at any of the rotary rings, thereby maximizing the operating frequency. Experimental results on benchmark circuits show that our method can reduce the tapping cost (measured as the total length of the wire segments connecting the rotary rings to the clock sinks) for rotary clocking by 33%-53% 相似文献
12.
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(9):1251-1256
13.
Systems for automated logic synthesis with the True Single Phase Clocking circuit technique (TSPC) and a modified form of the Clock and Data Precharged Dynamic (CDPD) circuit technique, are presented. The CDPD system synthesizes high speed one clock cycle modules of unate Boolean functions in short design time. A novel true single phase clocking (TSPC) flip-flop suitable for CDPD synthesis simplifies interfacing with standard edge triggered clocking schemes. Also, a TSPC cell library for automatic logic synthesis with the TSPC circuit technique is presented. The library is targeted for high performance DSP applications. Fabricated test circuits synthesized by both the CDPD and TSPC synthesis systems in a 0.8m standard CMOS process are described and their performance is verified. Clock frequencies up to 700MHz were measured. 相似文献
14.
A two-phase clocking scheme for rapid single flux quantum logic circuits, in particular, shift registers and correlators, is discussed. The two-phase pulse clock is generated on chip with one external clock line. The use of a two-phase clock improves the clock operating margins and eliminate the racethrough problem. A 32-b shift register has been built and tested up to a clock frequency of 21.6 GHz. A one-bit digital correlator with 32 stages has also been tested at low speed. The chips are fabricated using a Nb process 相似文献
15.
16.
Mohanty S.P. Ranganathan N. 《IEEE transactions on circuits and systems. I, Regular papers》2005,52(6):1157-1165
In low-power design for deep submicrometer and nanometer regimes, peak power, power fluctuation, average power, and total energy are equally important design constraints. In this paper, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power. The minimization schemes based on integer linear programming are developed for the design of datapaths that can function in three modes of operation: 1) single supply voltage and single frequency; 2) multiple supply voltages and dynamic frequency clocking (MVDFC); and 3) multiple supply voltages and multicycling. The techniques are evaluated by estimating the peak power consumption, the average power consumption and the power delay product of selected high level synthesis benchmark circuits for different resource constraints. Experimental results indicate that combining multiple voltages and dynamic frequency clocking as in the MVDFC scheme, yields significant reductions in the peak power, the average power, and the power delay product. 相似文献
17.
Riadul Islam 《Journal of Electronic Testing》2018,34(4):471-485
An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and die sizes. The technology scaling followed Moore’s law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flip-flops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C2-DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Post-layout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1–5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs. 相似文献
18.
Ki-Won Lee Joo-Hwan Cho Byoung-Jin Choi Geun-Il Lee Ho-Don Jung Woo-Young Lee Ki-Chon Park Yong-Suk Joo Jae-Hoon Cha Young-Jung Choi Moran P.B. Jin-Hong Ahn 《Solid-State Circuits, IEEE Journal of》2007,42(11):2369-2377
Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog delay-locked loop which provides a stable I/O clock and has 31.67 ps peak-to-peak jitter characteristics is designed. On the basis of these circuit techniques, the data rate is 3.2 Gbps/pin, which corresponds to 12.8 Gbps in times32 GDDR4-based I/O. Also, a multidivided architecture consisting of four independent 128 Mb core arrays is designed to reduce power line and output noise. 相似文献
19.
This paper describes RF1 and RF2, two level-clocked test-chips that deploy resonant clocking to reduce power consumption in their clock distribution networks. It also highlights RCL, a novel resonant-clock latch-based methodology that was used to design the two test-chips. RF1 and RF2 are 8-bit 14-tap finite-impulse response (FIR) filters with identical architectures. Designed using a fully automated ASIC design flow, they have been fabricated in a commercial 0.13 mum bulk silicon process. RF1 operates at clock frequencies in the 0.8-1.2 GHz range and uses a single-phase clocking scheme with a driven clock generator. Resonating its 42 pF clock load at 1.03 GHz with Vdd = 1.13 V, RF1 dissipates 132 mW, achieving a clock power reduction of 76% over conventional switching. RF2 achieves higher clock power efficiency than RF1 by relying on a two-phase clocking scheme with a distributed self-resonant clock generator. Resonating 38 pF of clock load per phase at 1.01 GHz with Vdd = 1.08 V, RF2 dissipates 124 mW and achieves 84% reduction in clock power over conventional switching. At 133 nW/MHz/Tap/InBit/CoeffBit, RF2 features the lowest figure of merit for FIR filters published to date. 相似文献
20.
A static frequency divider designed in a 210-GHz f/sub T/, 0.13-/spl mu/m SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input). 相似文献